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The Very Long Instruction Word (VLIW) architectures used this philosophy. The most famous of which is Intel's Itanium ISA. It turns out that it is really hard
by benjaminl 9y ago
The Very Long Instruction Word (VLIW) architectures used this philosophy. The most famous of which is Intel's Itanium ISA.
It turns out that it is really hard to create a compiler to effectively take advantage of instruction level parallelism at compile time.
- dnautics 9y agoyou mean.... it's really hard to create a non-x86 compiler that posts good results on {benchmarks designed to make x86 look good} if you're Intel. And/or no one can really be bothered to make their compile particularly well to a proprietary foreign architecture if the chip already costs an arm and a leg.
- philipkglass 9y agoit's really hard to create a non-x86 compiler that posts good results on {benchmarks designed to make x86 look good} if you're Intel. When I used Itanium 2 systems for HPC, Intel's compilers produced the fastest binaries from C and Fortran, at least on the software I used (molecular dynamics and quantum chemistry). What's meant by "benchmarks designed to make x86 look good"? Itanium was introduced against POWER, Alpha, SPARC, and MIPS chips. It was primarily benchmarked for server/workstation applications, where x86 processors weren't the fastest at the time. In 2003 a "Madison" Itanium 2 was significantly faster on numerical simulation code than a contemporary "Gallatin" x86 Xeon.
- jasonwatkinspdx 9y agoIt was worse than that. The archives of comp.lang.arch have a lot of detailed discussions on the gory details, including participation by senior designers at Intel among others. Itanium 2 did finally get reasonable performance, but only by adding back in dynamic scheduling to the microarchitecture. (This is all in terms of fundamental benchmarks that are not x86 specific).