4 ms·
Yes, I am about 2/3rds of the way through designing and building a single cycle, modified Harvard architecture, RV32E CPU. You can check it out here... https:/
by PhilWright 9y ago
Yes, I am about 2/3rds of the way through designing and building a single cycle, modified Harvard architecture, RV32E CPU. You can check it out here...
https://hackaday.io/project/18491-worlds-first-32-bit-homebrew-cpu https://hackaday.io/project/18491-worlds-first-32-bit-homebr...
Although a projected speed of 1Mhz and the size might exclude it from your own project!
- gok 9y agoI meant more like... just using straight Verilog, but very impressive!
- dnautics 9y agoI'm not sure I would recommend using straight verilog for something of that magnitude. I do know that some folks that used Perl to assemble verilog into a computer chip, but they regretted the engineering debt that came with it (and the hire they made that instituted that decision).
- senatorobama 9y ago> Perl to assemble verilog into a computer chip This is absurdly common.