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So is anyone designing RISC-V cores without using Chisel? :)
by gok 9y ago
So is anyone designing RISC-V cores without using Chisel? :)
- PhilWright 9y agoYes, I am about 2/3rds of the way through designing and building a single cycle, modified Harvard architecture, RV32E CPU. You can check it out here... https://hackaday.io/project/18491-worlds-first-32-bit-homebrew-cpu https://hackaday.io/project/18491-worlds-first-32-bit-homebr... Although a projected speed of 1Mhz and the size might exclude it from your own project!
- gok 9y agoI meant more like... just using straight Verilog, but very impressive!
- dnautics 9y agoI'm not sure I would recommend using straight verilog for something of that magnitude. I do know that some folks that used Perl to assemble verilog into a computer chip, but they regretted the engineering debt that came with it (and the hire they made that instituted that decision).
- senatorobama 9y ago> Perl to assemble verilog into a computer chip This is absurdly common.
- rjsw 9y agoThere is PicoRV32 [1]. [1] https://github.com/cliffordwolf/picorv32 https://github.com/cliffordwolf/picorv32
- cbHXBY1D 9y agoYep and there's https://github.com/SpinalHDL/VexRiscv https://github.com/SpinalHDL/VexRiscv But admittedly, SpinalHDL is basically Chisel.
- cmrx64 9y agoplenty. not as many open source ones though.
- vanjoe 9y agoYeah there are a few out there. At Vectorblox we have ORCA that we use as a cross-platform replacement for nios/microbaze. I don't know of anyone who has built anything as sophisticated as BOOM though.
- chas 9y agoHere's a collection of RISC-V cores in Bluespec: https://github.com/csail-csg/riscy https://github.com/csail-csg/riscy
- evancox10 9y agoYes, see Syntacore's SCR1, Clifford Wolf's PicoRV32,etc. Granted these are smaller, microcontroller-class cores, but still in pure Verilog. I'm sure there are others out there with more/less performance
- trynumber9 9y agoNvidia said they're not using Chisel for the RISC-V cores they plan to embed in their GPUs. see https://www.youtube.com/watch?v=g6Z_5l69keI&t=545 https://www.youtube.com/watch?v=g6Z_5l69keI&t=545
- razer6 9y agoThere is the PULP project (http://www.pulp-platform.org/ http://www.pulp-platform.org/) by ETH Zurich and University of Bologna with different open-source RISCV cores written in (System) Verilog.