2 ms·

In analogue hardware implementations spike events are transmitted on a standard digital bus using AER (address-event representation). The signal is not attenuat

In analogue hardware implementations spike events are transmitted on a standard digital bus using AER (address-event representation). The signal is not attenuated, since standard digital hardware (though asynchronous, depending on the implementation) is used to transmit the spike. Spurious noise injection is thus not a significant problem as well. Note that I'm only a layman when it comes to analogue neuromorphic hardware implementation details, I encourage you to have a look at [1] for more detailed energy computations. [1] http://web.stanford.edu/group/brainsinsilicon/documents/IEEE2017.pdf http://web.stanford.edu/group/brainsinsilicon/documents/IEEE... Edit: Added a "significant" above. There indeed are minor problems with cross talk causing additional spikes, but mostly in the analogue neuron subthreshold regime, not in the AER bus. [2] [2] http://journal.frontiersin.org/article/10.3389/fncom.2017.00071/full http://journal.frontiersin.org/article/10.3389/fncom.2017.00...

p1esk 9y ago
Wait a second, so your solution is a digital shared bus? With a need to look stuff up in a separate RAM block? Do you realize that this is pretty much the worst thing from an energy efficiency standpoint? I've looked at the NeuroGrid link. It's still not clear to me why they want to use spikes. Some parts of their design decisions (e.g. AER bus) are forced by the need to deal with spikes, and it feels like their hardware architecture would be simpler and more efficient if they didn't. Is the only reason "biological plausibility"? Ultimately, what we want is hardware that can do what my 250 Watts 1080Ti card does (e.g. reach high classification accuracy on ImageNet) but faster and using less less power. Spikes don't seem like the best approach to achieve that.

2 ms·

In analogue hardware implementations spike events are transmitted on a standard digital bus using AER (address-event representation). The signal is not attenuat

by aurelian15 9y ago

p1esk 9y ago
Wait a second, so your solution is a digital shared bus? With a need to look stuff up in a separate RAM block? Do you realize that this is pretty much the worst thing from an energy efficiency standpoint? I've looked at the NeuroGrid link. It's still not clear to me why they want to use spikes. Some parts of their design decisions (e.g. AER bus) are forced by the need to deal with spikes, and it feels like their hardware architecture would be simpler and more efficient if they didn't. Is the only reason "biological plausibility"? Ultimately, what we want is hardware that can do what my 250 Watts 1080Ti card does (e.g. reach high classification accuracy on ImageNet) but faster and using less less power. Spikes don't seem like the best approach to achieve that.