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You're right that analogue non-spiking hardware in theory would be the way to go for deep neural networks. However, when implemented in a modern semiconductor

You're right that analogue non-spiking hardware in theory would be the way to go for deep neural networks. However, when implemented in a modern semiconductor process, it is relatively hard to implement analogue computations with negligible noise; especially when connecting distant parts of the chip. Spiking neuron models have the advantage of producing digital output (either they are spiking at a given moment in time or they don't). Thus this pulse can be easily transported without information loss, and the analogue computation is confined to a relatively small region, which makes it possible to reduce noise in the internal analogue signals. A different way to think about it: say you wanted to implement an analogue model of a classical neuron (as used in deep neural nets) and wanted to transfer its output as a digital signal to mitigate the noise problem. In that case, the required analogue/digital converter would be far more complex than the analogue neuron itself. As you continue to reduce the size and precision of the A/D converter you'd end up with a 1-bit delta-sigma A/D converter, and you're circuit would very much look like a spiking neuron. Edit: Reformulated some parts for clarity

p1esk 9y ago
In an ideal world, yes a spike would be a simple binary signal, easy to generate/detect. Unfortunately, in the world we live in, it's quite a bit more complicated. Have you ever looked at Spice simulations where you needed to propagate a pulse (a spike with duration of one clock cycle)? It quickly gets distorted and attenuated. I don't see how noise in the circuit is anything less of a problem for a spike than it is for a constant signal. It actually seems to be more susceptible to noise, because now some spurious noise injection could be interpreted as a spike by the receiver! What makes you think short pulses are more noise resistant than long ones? And if you try to utilize interspike timings to encode information you expose yourself to a whole bunch of additional challenges (not sure if those timings are used in the current spiking network models though).
- aurelian15 9y ago
  In analogue hardware implementations spike events are transmitted on a standard digital bus using AER (address-event representation). The signal is not attenuated, since standard digital hardware (though asynchronous, depending on the implementation) is used to transmit the spike. Spurious noise injection is thus not a significant problem as well. Note that I'm only a layman when it comes to analogue neuromorphic hardware implementation details, I encourage you to have a look at [1] for more detailed energy computations. [1] http://web.stanford.edu/group/brainsinsilicon/documents/IEEE2017.pdf http://web.stanford.edu/group/brainsinsilicon/documents/IEEE... Edit: Added a "significant" above. There indeed are minor problems with cross talk causing additional spikes, but mostly in the analogue neuron subthreshold regime, not in the AER bus. [2] [2] http://journal.frontiersin.org/article/10.3389/fncom.2017.00071/full http://journal.frontiersin.org/article/10.3389/fncom.2017.00...
  - p1esk 9y ago
    Wait a second, so your solution is a digital shared bus? With a need to look stuff up in a separate RAM block? Do you realize that this is pretty much the worst thing from an energy efficiency standpoint? I've looked at the NeuroGrid link. It's still not clear to me why they want to use spikes. Some parts of their design decisions (e.g. AER bus) are forced by the need to deal with spikes, and it feels like their hardware architecture would be simpler and more efficient if they didn't. Is the only reason "biological plausibility"? Ultimately, what we want is hardware that can do what my 250 Watts 1080Ti card does (e.g. reach high classification accuracy on ImageNet) but faster and using less less power. Spikes don't seem like the best approach to achieve that.

p1esk 9y ago

In an ideal world, yes a spike would be a simple binary signal, easy to generate/detect. Unfortunately, in the world we live in, it's quite a bit more complicated. Have you ever looked at Spice simulations where you needed to propagate a pulse (a spike with duration of one clock cycle)? It quickly gets distorted and attenuated. I don't see how noise in the circuit is anything less of a problem for a spike than it is for a constant signal. It actually seems to be more susceptible to noise, because now some spurious noise injection could be interpreted as a spike by the receiver! What makes you think short pulses are more noise resistant than long ones? And if you try to utilize interspike timings to encode information you expose yourself to a whole bunch of additional challenges (not sure if those timings are used in the current spiking network models though).

aurelian15 9y ago
In analogue hardware implementations spike events are transmitted on a standard digital bus using AER (address-event representation). The signal is not attenuated, since standard digital hardware (though asynchronous, depending on the implementation) is used to transmit the spike. Spurious noise injection is thus not a significant problem as well. Note that I'm only a layman when it comes to analogue neuromorphic hardware implementation details, I encourage you to have a look at [1] for more detailed energy computations. [1] http://web.stanford.edu/group/brainsinsilicon/documents/IEEE2017.pdf http://web.stanford.edu/group/brainsinsilicon/documents/IEEE... Edit: Added a "significant" above. There indeed are minor problems with cross talk causing additional spikes, but mostly in the analogue neuron subthreshold regime, not in the AER bus. [2] [2] http://journal.frontiersin.org/article/10.3389/fncom.2017.00071/full http://journal.frontiersin.org/article/10.3389/fncom.2017.00...
- p1esk 9y ago
  Wait a second, so your solution is a digital shared bus? With a need to look stuff up in a separate RAM block? Do you realize that this is pretty much the worst thing from an energy efficiency standpoint? I've looked at the NeuroGrid link. It's still not clear to me why they want to use spikes. Some parts of their design decisions (e.g. AER bus) are forced by the need to deal with spikes, and it feels like their hardware architecture would be simpler and more efficient if they didn't. Is the only reason "biological plausibility"? Ultimately, what we want is hardware that can do what my 250 Watts 1080Ti card does (e.g. reach high classification accuracy on ImageNet) but faster and using less less power. Spikes don't seem like the best approach to achieve that.