> All CPUs (two in the previous example, but there can be more) are connected via a common bus (the Front Side Bus, FSB) to the Northbridge. This is very out o

> All CPUs (two in the previous example, but there can be more) are connected via a common bus (the Front Side Bus, FSB) to the Northbridge. This is very out of date. The Northbridge was pushed onto the CPU die about the time that the article was written (2007). I'm not sure exactly what consequence that has but I suspect it invalidates a large chunk of the discussion. Modern memory controllers (which are on the CPU die and evolved out of what used to be the Northbridge) have various fancy features that weren't available in 2007. For examples: 1. DDIO. Without this, when a PCIe device DMAs data into system RAM, you are very likely to get a cache miss when the CPU reads the data because the data was written into DRAM and not the CPU cache. DDIO writes it into the CPU cache. This is quite important for modern networking, where the packet interval can be less than the time taken for a cache miss. (https://www.intel.co.uk/content/www/uk/en/io/data-direct-i-o-technology.html https://www.intel.co.uk/content/www/uk/en/io/data-direct-i-o...) 2. These days a single CPU has many cores, hyperthreading and deep-speculative execution abilities. As a result, the CPU can post many reads into the memory subsystem in parallel. The memory controller keeps a table of who's reading what, so that it can optimize DRAM access - eg two independent reads can be scheduled together if they happen to target the same DRAM row. Checkout my boring question on Stackoverflow (https://stackoverflow.com/questions/45382914/parallel-memory-access-on-modern-processors https://stackoverflow.com/questions/45382914/parallel-memory...).