I think this is very interesting, and certainly consider myself a "fan" of the RISC-V ISA and project. Great to see cheaper/smaller boards coming along. I'm st

I think this is very interesting, and certainly consider myself a "fan" of the RISC-V ISA and project. Great to see cheaper/smaller boards coming along. I'm still hoping they can somehow get access to a flash process, so that they can integrate the CPU core (and peripherals, of course) with the flash in the same chip. This board still uses QSPI to talk to an external flash, which houses the code. I'm not sure how programming is done, with "traditional" microcontrollers that have their own flash, you use JTAG (or even serial on the older ones) to program the flash directly, then just remove the JTAG lines and reset the board and it runs your code. With this, I guess you have to program the SPI flash directly, or (perhaps?) use JTAG to talk to the microcontroller core and control its SPI that way? Anyway, my understanding is that flash memory is "deep analog magic" which the people behind RISC-V haven't mastered yet, so they can't design the memory into the same chip as the processor core.