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Slightly off topic, but are there more-or-less boilerplate RISC-V verilog/VHDL designs available that can deploy to ~$100ish FPGA boards? I'd be super intereste
by spilk 9y ago
Slightly off topic, but are there more-or-less boilerplate RISC-V verilog/VHDL designs available that can deploy to ~$100ish FPGA boards? I'd be super interested in messing with that if so. I took digital design and HDL related courses in university but haven't really had an opportunity to do anything productive with that yet.
- peller 9y agoI have no experience with any of this, but to my knowledge what you're looking for is the Rocket Chip.[0] It's a RISC-V core implemented in Chisel. The primary FPGA target is a bit steep at around $500 [1] but there's a "small" config[2] that targets a more reasonable $190 board [3]. [0] https://github.com/freechipsproject/rocket-chip https://github.com/freechipsproject/rocket-chip [1] http://store.digilentinc.com/zedboard-zynq-7000-arm-fpga-soc-development-board/ http://store.digilentinc.com/zedboard-zynq-7000-arm-fpga-soc... [2] https://github.com/freechipsproject/rocket-chip#-how-can-i-parameterize-my-rocket-chip https://github.com/freechipsproject/rocket-chip#-how-can-i-p... [3] http://store.digilentinc.com/zybo-zynq-7000-arm-fpga-soc-trainer-board/ http://store.digilentinc.com/zybo-zynq-7000-arm-fpga-soc-tra...
- zokier 9y agoQuickly googling I found two (edit: three) RISC-V cores that can target ice40, which is small/cheap fpga. It's of special interest because it has foss toolchain available
- jsolson 9y agoOpenCores probably has something. I don't know about RISC-V, specifically. On a semi-related note, I was surprised at how little area the ARM Design Start Cortex-M0 took up out of an Artix 35T. FPGAs have gotten big and simple CPUs are tiny :)
- TomV1971 9y agoYou can run a PicoRV32 on a dirt cheap Altera EP2C5 Cyclone 2 board. I have the RioRand® EP2C5T144 Altera Cyclone II FPGA Mini Development Board ($23 on Amazon). You'll also need a clone of a USB blaster JTAG cable, which goes for $10 or less.