3 ms·

I guess a more accurate statement would be "no practical digital logic design can work without clock (unless you are doing seldom used, generally undesirable as

by tonmoy 9y ago

I guess a more accurate statement would be "no practical digital logic design can work without clock (unless you are doing seldom used, generally undesirable asynchronous design)" HDL languages do have loops, but they are for testbench purposes only, in hardware implemention non generate loops would not be implemented! I think by saying "Everything happens at once" the author meant that all your code executes at once. He is obviously trying to get the one line at a time sequential mindset out from people used with software.

forthfifthsixth 9y ago
I don't think asynchronous logic is undesirable. For an example, the GA144[1] is an example of a practical computer completely implemented asynchronous logic. Its Asynchronous nature is one of the features, benefits include lower power consumption, faster speed, and lower electromagnetic interference [1]http://www.greenarraychips.com/home/documents/greg/PB001-100503-GA144-1-10.pdf http://www.greenarraychips.com/home/documents/greg/PB001-100...
- tonmoy 9y ago
  I meant undesireable in the sense that it takes longer time to develop and harder to debug, but you are absolutely right about the power consumption and speed
DigitalJack 9y ago
I would have said synchronous digital logic requires a clock. Clearly combinational logic does not. The type of design you do is purely dependent on your needs. Asynchronous design is neither good or bad. It's what you need or it isn't. Here is a perfectly fine, synthesizable parity generator using a non generative for loop (vhdl): library ieee; use ieee.std_logic_1164.all; entity for_parity is port (input : in std_logic_vector (7 downto 0); even : out std_logic; odd : out std_logic); end for_parity ; architecture for_arch of for_parity is signal even_parity : std_logic; begin calc: process (input) is variable temp : std_logic; begin temp := '0'; for i in 0 to 7 loop temp:=temp xor input(i); end loop; even_parity <= temp; end process calc; even <= even_parity; odd <= (not even_parity); end for_arch; As for the last point, I make extensive use of sequential logic, a concept made possible by delays through transistors, and I can't think of a more confusing thing to say to someone than "it all happens at once" because it does not.

by tonmoy 9y ago

forthfifthsixth 9y ago

I don't think asynchronous logic is undesirable. For an example, the GA144[1] is an example of a practical computer completely implemented asynchronous logic. Its Asynchronous nature is one of the features, benefits include lower power consumption, faster speed, and lower electromagnetic interference [1]http://www.greenarraychips.com/home/documents/greg/PB001-100503-GA144-1-10.pdf http://www.greenarraychips.com/home/documents/greg/PB001-100...

tonmoy 9y ago
I meant undesireable in the sense that it takes longer time to develop and harder to debug, but you are absolutely right about the power consumption and speed

DigitalJack 9y ago

I would have said synchronous digital logic requires a clock. Clearly combinational logic does not. The type of design you do is purely dependent on your needs. Asynchronous design is neither good or bad. It's what you need or it isn't. Here is a perfectly fine, synthesizable parity generator using a non generative for loop (vhdl): library ieee; use ieee.std_logic_1164.all; entity for_parity is port (input : in std_logic_vector (7 downto 0); even : out std_logic; odd : out std_logic); end for_parity ; architecture for_arch of for_parity is signal even_parity : std_logic; begin calc: process (input) is variable temp : std_logic; begin temp := '0'; for i in 0 to 7 loop temp:=temp xor input(i); end loop; even_parity <= temp; end process calc; even <= even_parity; odd <= (not even_parity); end for_arch; As for the last point, I make extensive use of sequential logic, a concept made possible by delays through transistors, and I can't think of a more confusing thing to say to someone than "it all happens at once" because it does not.