My favorite bit: L2 instruction cache that also has an on-chip interconnect that links the clusters and caches to each other as well as packet storage, acceler

My favorite bit: L2 instruction cache that also has an on-chip interconnect that links the clusters and caches to each other as well as packet storage, accelerators, on-chip memories, and DRAM controllers together. This interconnect runs at 1 GHz and has more than 9 Tb/sec of aggregate bandwidth I keep seeing elephant guns and experimental German artillery when I read that!