My understanding is that they are included. The paper talks about the problem it is addressing in Section 2. The following text is taken from that section and m

My understanding is that they are included. The paper talks about the problem it is addressing in Section 2. The following text is taken from that section and makes me think that extra moves/exchanges introduced by out-of-SSA are included. > Live-range splitting to handle register constraints and φ-functions make use of parallel copy instructions. These parallel copy instructions have of course to be implemented using real processor instructions (in the case of φ-functions this is called SSA destruction [5]). In contrast to traditional approaches, these parallel copies are implemented after register allocation and not before. [...] the goal of coalescing is to minimize the number of instructions to implement parallel copies by trying to give corresponding operands and results the same color.