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I wish I could bet money on this not happening "by February". Dude is promising perf that's 25% higher than Titan X Pascal in a power envelope that's 1/50th of
by 0xbear 9y ago
I wish I could bet money on this not happening "by February". Dude is promising perf that's 25% higher than Titan X Pascal in a power envelope that's 1/50th of Titan X Pascal, and he's promising to do it with a few tens of millions of dollars and a handful of people.
Yeah, right. Like that's ever going to happen. Sounds like the usual grandiose claims to get clueless moneybags to pony up the cash for series B.
- jamiek88 9y agoYeah, extraordinary claims and all that. Especially as this guy has a credibility problem in the first place because of the ML cheating scandal from a few years ago (1) he was in the middle of. 15 tflops of even 3x3 stacked in 5 watts? 'Taped out by Feb' - I am sceptical to say the least. (1) https://www.enterprisetech.com/2015/06/12/baidu-fires-deep-images-ren-wu/ https://www.enterprisetech.com/2015/06/12/baidu-fires-deep-i...
- rayuela 9y agoOh wow I had not realized that was him. That was pretty bad, what they were doing was outright dishonest. I wouldn't trust them with a dime of my money.
- dnautics 9y agoIt's not impossible. I've seen a company go from zero to tapeout in six months. However, they did wind up getting stuck due to bugs on the motherboard. (the chip did work)
- deepnotderp 9y agoIt's totally possible with a few million dollars and a couple of guys, especially for a chip this simple. See for example the Adapteva Epiphany (one guy on 16nm) and Rex Computing.
- 0xbear 9y agoBut the chip is _not_ simple. You can't get 15TFLOPS with a "simple" chip. Even TPU1 is not simple and it took Google over 2 years to get that from the drawing board to the data centers. Moreover, 15TFLOPS, in the unlikely event that they design and build it, is not going to be 5W. Unless they know something the likes of Intel, NVIDIA etc don't know. The probability of that is not just vanishingly small, it's zero.
- deepnotderp 9y agoThe chip, from a design perspective, can absolutely be simple and get 15 TFLOPs. And in 5W is totally possible (in fact, greater efficiency is possible), especially if you only restrict yourself to inference with 3x3 convolutions. And it's not at all impossible that they know something that Intel/nVidia doesn't, that's how innovation from startups work ;) And as to their power efficiency number, it's not just possible, but it's possible to do even better than that, as we have. And these processors are definitely simpler than say, an OoO CPU. Note that I mean this from a design perspective, from an innovation perspective, it's your call as to whether or not it's "simple".
- 0xbear 9y ago15TFLOPS at 1Ghz is 15KFLOPS per cycle, every cycle, pipelined to amortize latency. And it's also sufficient cache and memory bandwidth to funnel data in and out of that thing at that speed, and keep the weight matrix close to the computation. This physically can't be simple. If my calculations are right, in order to realize 15TFLOPS on a 3x3 conv of a 224x224x32 layer with a filter bank of 64 filters you'd need 117.2GB/s of sustained memory bandwidth just to read the inputs, and twice that to write the output. Good luck achieving that with 5 watts and in 6 months.
- deepnotderp 9y agoUhhh, 117.2 GB/s isn't hard at all on die, getting ~10X that amount is possible even through the HBM2 bus. Instead of downvoting me, can you actually present a technical argument? Have you ever designed a chip or taped one out? And yes, physically it definitely is indeed simple (what would you consider a "complex" processor and a "simple" processor?). Plus these processors aren't using caches, there's no need for them.
- dboreham 9y agoThere should be an options market for "shorting bullshit".