In case of the i.MX6 SoC I do the training and calibration and the recommended register values obtained is provided to U-boot. So now when U-boot starts up it s

In case of the i.MX6 SoC I do the training and calibration and the recommended register values obtained is provided to U-boot. So now when U-boot starts up it starts on the SoC inbuilt SRAM which is very less (a few kilobytes). Once the first stage U-boot is booted it sets up the memory controller registers and the boots using this RAM. When the DDR/LPDDR training happens it is supposed to be left overnight for multiple iterations. Temperature also matters for proper values and hence one of the reasons the multiple iteration testing done overnight. In my case I had some really incompetent board designers who were just blaming. Finally since there might have been layout issues I was forced to lower the clock speeds (halve the clocks) for the DDR interfacing.