3 ms·

> Is this the seemingly-pointless "memory test" all computers do? I might not be sure what your parent is talking but it is called "DDR memory training and cal

> Is this the seemingly-pointless "memory test" all computers do? I might not be sure what your parent is talking but it is called "DDR memory training and calibration". I used to struggle with this when I was bringing up LPDDR2 on an i.MX6 embedded board. You can find more about it here -> https://github.com/librecore-org/librecore/wiki/Understanding-DDR-Memory-Training https://github.com/librecore-org/librecore/wiki/Understandin...

exikyut 9y ago
Wow. Really, really impressive. How far back did BIOSes do this - has it always been done?(!) I can completely understand it being a struggle now. At some point was I thinking of getting into tinkering with DDR3/4 on FPGAs (to play with some video capture ideas), but I'm beginning to not look forward to it... heheh
- mindentropy 9y ago
  I don't have advanced BIOS and most of the BIOS uses a safe set of values is my assumption. However BIOSes catered to overclocking crowd has this functionality. Ref1: http://www.overclock.net/t/1490835/the-gigabyte-z97x-overclocking-guide http://www.overclock.net/t/1490835/the-gigabyte-z97x-overclo... Ref2: http://www.tomshardware.co.uk/ram-overclocking-guide,review-33633-3.html http://www.tomshardware.co.uk/ram-overclocking-guide,review-... Also remember that the training also depends on the environmental temperature. > I can completely understand it being a struggle now. At some point was I thinking of getting into tinkering with DDR3/4 on FPGAs Understanding of the different values for the registers which the tool recommends and validating the value is a real pain although some of the vendors such as Micron's datasheets explains things nicely. Xilinx MIG has a really dense guide and you really need to understand your timing etc. It is really not for the faint hearted.
- mindentropy 9y ago
  In case of the i.MX6 SoC I do the training and calibration and the recommended register values obtained is provided to U-boot. So now when U-boot starts up it starts on the SoC inbuilt SRAM which is very less (a few kilobytes). Once the first stage U-boot is booted it sets up the memory controller registers and the boots using this RAM. When the DDR/LPDDR training happens it is supposed to be left overnight for multiple iterations. Temperature also matters for proper values and hence one of the reasons the multiple iteration testing done overnight. In my case I had some really incompetent board designers who were just blaming. Finally since there might have been layout issues I was forced to lower the clock speeds (halve the clocks) for the DDR interfacing.

exikyut 9y ago

Wow. Really, really impressive. How far back did BIOSes do this - has it always been done?(!) I can completely understand it being a struggle now. At some point was I thinking of getting into tinkering with DDR3/4 on FPGAs (to play with some video capture ideas), but I'm beginning to not look forward to it... heheh

mindentropy 9y ago
I don't have advanced BIOS and most of the BIOS uses a safe set of values is my assumption. However BIOSes catered to overclocking crowd has this functionality. Ref1: http://www.overclock.net/t/1490835/the-gigabyte-z97x-overclocking-guide http://www.overclock.net/t/1490835/the-gigabyte-z97x-overclo... Ref2: http://www.tomshardware.co.uk/ram-overclocking-guide,review-33633-3.html http://www.tomshardware.co.uk/ram-overclocking-guide,review-... Also remember that the training also depends on the environmental temperature. > I can completely understand it being a struggle now. At some point was I thinking of getting into tinkering with DDR3/4 on FPGAs Understanding of the different values for the registers which the tool recommends and validating the value is a real pain although some of the vendors such as Micron's datasheets explains things nicely. Xilinx MIG has a really dense guide and you really need to understand your timing etc. It is really not for the faint hearted.
mindentropy 9y ago
In case of the i.MX6 SoC I do the training and calibration and the recommended register values obtained is provided to U-boot. So now when U-boot starts up it starts on the SoC inbuilt SRAM which is very less (a few kilobytes). Once the first stage U-boot is booted it sets up the memory controller registers and the boots using this RAM. When the DDR/LPDDR training happens it is supposed to be left overnight for multiple iterations. Temperature also matters for proper values and hence one of the reasons the multiple iteration testing done overnight. In my case I had some really incompetent board designers who were just blaming. Finally since there might have been layout issues I was forced to lower the clock speeds (halve the clocks) for the DDR interfacing.