In fact it is CPU thing since x86 CPUs have on-die caches, because the masking has to happen before the access hits cache. Nehalem removed the physical pin for

In fact it is CPU thing since x86 CPUs have on-die caches, because the masking has to happen before the access hits cache. Nehalem removed the physical pin for outside control of that feature (for the northbridge/southbridge platforms this involved a wire that went directly from CPU to EC/SuperIO connected to LPC or ISA, which is highly weird from architectural standpoint).