2 ms·

> Just to clarify: the A20 stuff was an IBM PC/AT feature in the chipset of the original machine, not a CPU thing. To quote https://en.wikipedia.org/w/index.ph

> Just to clarify: the A20 stuff was an IBM PC/AT feature in the chipset of the original machine, not a CPU thing. To quote https://en.wikipedia.org/w/index.php?title=A20_line&oldid=795257485#A20_gate https://en.wikipedia.org/w/index.php?title=A20_line&oldid=79... "Support for the A20 gate was changed in the Nehalem microarchitecture (some sources incorrectly claim A20 support was removed). Rather than the CPU having a dedicated A20M# pin which receives the signal whether or not to mask the A20 bit, it has been virtualized so that the information is sent from the peripheral hardware to the CPU using special bus cycles." So it is now a CPU thing.

dfox 9y ago
In fact it is CPU thing since x86 CPUs have on-die caches, because the masking has to happen before the access hits cache. Nehalem removed the physical pin for outside control of that feature (for the northbridge/southbridge platforms this involved a wire that went directly from CPU to EC/SuperIO connected to LPC or ISA, which is highly weird from architectural standpoint).