Here are some more rules I like to use: Use I/O flip flops: the external world should be separated from the internal world via one pipeline stage, and that sta

Here are some more rules I like to use: Use I/O flip flops: the external world should be separated from the internal world via one pipeline stage, and that stage should be in the I/O cells. This is not always easy to pull off (Xilinx, ugh), but when you do it you will get consistent I/O timing from run to run, and basically not have to worry about it once it's working. It's less error-prone than trying to have accurate external timing constraints. This is really for older (board-level) synchronous designs. Often the FPGA and board designs are happening at the same time. Get a skeleton design working before the board design is complete. This design should include all I/O, clocks and resets. There can be many non-obvious constraints involving these things, so you better have them right before the board design is done or you are in for a world of hurt. Along the same lines: take baby steps during the design (get blinking LEDs and some kind of software accessible register interface running first). Oh a big one: use version control. Unfortunately the tools (Xilinx) do not make this easy, but it is really essential. You would be surprised at how often this is not done.