3 ms·

>Do not use an asynchronous reset within your design It's not bad advice for new designers, but also be aware of the consequences: you might have a performance

>Do not use an asynchronous reset within your design It's not bad advice for new designers, but also be aware of the consequences: you might have a performance penalty from this if your FPGA's flip flops do not have direct synchronous resets. Also if your design might have to be ported to an ASIC you might have the same issue. Better is to use the "asynchronous assert, synchronous release" reset and learn about recovery and removal timing closure. In the past I've also designed with no timing requirements on reset, but start out all state machines doing nothing, and have a (synchronous) start pulse or edge to get things going. This can allow you to use the already existing slow global reset net. It mattered on older FPGAs with limited routing resources.

kevin_thibedeau 9y ago
> Better is to use the "asynchronous assert, synchronous release" reset Also put that synchronized async. reset onto a clock buffer if your synthesis tool isn't inferring one since it will be a high fanout net. For an FPGA target you lose most of the benefits from synchronizing it if you let the reset be delayed by running over the normal routing fabric. For an ASIC you're going to have to buffer it no matter what. A common problem is that most FPGA dev. boards don't have any provision for an external reset and student's never learn the discipline of properly initializing their circuits. Xilinx takes an official stance against global resets [1] which I feel does untold damage to impressionable developers. Thankfully they do have the ROC library component that will simulate a reset after completion of configuration. Use this or your platform's equivalent if you don't have access to an external reset. [1] https://www.xilinx.com/support/documentation/white_papers/wp272.pdf https://www.xilinx.com/support/documentation/white_papers/wp...
sweden 9y ago
I would say that not using asynchronous reset is very very advice. Sometimes the clock is not even available to the system in the beginning of execution.

kevin_thibedeau 9y ago

> Better is to use the "asynchronous assert, synchronous release" reset Also put that synchronized async. reset onto a clock buffer if your synthesis tool isn't inferring one since it will be a high fanout net. For an FPGA target you lose most of the benefits from synchronizing it if you let the reset be delayed by running over the normal routing fabric. For an ASIC you're going to have to buffer it no matter what. A common problem is that most FPGA dev. boards don't have any provision for an external reset and student's never learn the discipline of properly initializing their circuits. Xilinx takes an official stance against global resets [1] which I feel does untold damage to impressionable developers. Thankfully they do have the ROC library component that will simulate a reset after completion of configuration. Use this or your platform's equivalent if you don't have access to an external reset. [1] https://www.xilinx.com/support/documentation/white_papers/wp272.pdf https://www.xilinx.com/support/documentation/white_papers/wp...

sweden 9y ago

I would say that not using asynchronous reset is very very advice. Sometimes the clock is not even available to the system in the beginning of execution.