3 ms·
Feasible? Very. Detrimental to performance on average, though. I remember sitting through many LP64 versus ILP64 meetings almost 20 years ago when the transit
by dbcurtis 9y ago
Feasible? Very. Detrimental to performance on average, though. I remember sitting through many LP64 versus ILP64 meetings almost 20 years ago when the transition to 64-bit was upon us. (At least upon us CPU designers...) Turns out 64 bit ints cause memory usage and cache pressure that outweigh the benefits.
A lot of people don't think about the effect of design decisions on cache performance. Die area devoted to cache can't be used for other things, and the process of filling the cache with larger entities impacts memory bandwidth utilization. So 64 bit ints when mostly you only need 32 bits can turn out to be a loser. This is also why the pendulum has swung back to CISC -- more functionality crammed into smaller cache footprint, and the compilers are much better at targeting CISC instruction sets than they were at the height of RISC.
- renox 9y agoI disagree with the last part of your comment: many RISC added a 16 bit extension of their ISA.. So you can have RISC and code density similar to CISC, no need to keep a bloated instruction decoder on the CPU..
- orbifold 9y agoThe instruction decoder is tiny compared to the rest of the components on the chip, it also can be (partially) autogenerated. I still don't want to be on the team doing that...
- deleted 9y ago[deleted]