Tristate buses are mostly a workaround for interconnect (pins on chips & wires on boards) being expensive. Early CPUs sometimes took it even further, using not

Tristate buses are mostly a workaround for interconnect (pins on chips & wires on boards) being expensive. Early CPUs sometimes took it even further, using not only tri-state but address/data latching; the 8008 is a classic example (8 data bits & 14 address bits output through a single byte-wide connection). The tradeoff in something like the 8008 is lower performance: the 22 bits required to form a full address + data pair need 3 clock cycles to travel from inside the CPU to the peripherals. What we see instead in FPGAs is "buses" like AMBA - unidirectional data & address, sometimes with wide paths for data (the Xilinx AXI4 generator claims up to 1024 bits). These let designers take advantage of plentiful interconnect to get more bandwidth without needing the underlying FPGA's clock rate to increase.