It is not well documented by anyone. However, the expectation is that it is a matrix or convolution coprocessor, as this is a common operation in deep neural ne

It is not well documented by anyone. However, the expectation is that it is a matrix or convolution coprocessor, as this is a common operation in deep neural networks (for both inference and training). For instance, NVIDIA says they are supporting 4x4 convolutions with the tensor unit.