3 ms·

Cached an uncached memory access are currently staticaly specified by range : https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/VexRiscv/demo/Br

by Dolu 9y ago

Cached an uncached memory access are currently staticaly specified by range : https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/VexRiscv/demo/Briey.scala#L234 https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/s... From 0xF000000 to 0xFFFFFFFF access will be uncached.