5 ms·
Yes, silicon implementation provide the JTAG, but it's very likely their implementation will not be reusable for FPGA project (including JTAG debug things) beca
by Dolu 9y ago
Yes, silicon implementation provide the JTAG, but it's very likely their implementation will not be reusable for FPGA project (including JTAG debug things) because of their over complicated (but powerfull) solutions which would consume way to much area and restrict the FMax.
Then this specific VexRiscv ecosystem also provide a basic SoC with an multi master AXI4 inteconnect, SDRAM controller, embedded ram, APB3 interconnect, some slave like GPIO, UART, Timer, VGA. It's not incredible, but it's already a starting point ^^
See https://github.com/SpinalHDL/VexRiscv#briey-soc https://github.com/SpinalHDL/VexRiscv#briey-soc
- duskwuff 9y agoFor an FPGA implementation, it's often useful to hook the soft core into the FPGA's own JTAG controller, so that it's possible to program the FPGA and debug the core over a single connection. This is often not portable even between FPGAs, and certainly isn't portable to ASIC, but it makes development a lot easier, so...
- Dolu 9y agoYes i agree, would have been more convenent to use the integrated jtag of the FPGA, but i focused on making an universal solution first :)
- zokier 9y agoIs either AXI4 or APB3 usable as external bus (like PCI(/e)), or are they intended for on-die communication?
- Dolu 9y agoThey aren't made for external com
- monocasa 9y agoThey are usable externally. The Realview boards use it to connect a CPU chip with an external northbridge, but it's really rare. Even in that case, it's just because the Realview board is meant to prototype SoCs with the help of an FPGA.
- duskwuff 9y agoUsable, but only barely. As AXI / APB3 are intended for on-die communications, they lack the line coding and error correction used by other busses like PCIe or SATA. On the upside, though, they take a lot less area to implement.
- monocasa 9y agoThat's more a distinction between serial and parallel buses than on-chip/off chip. If you're not pumping a single signal to gbps speeds, you don't need the clock recovery and ECC that serdes style connections imply. It all depends on your use case.
- bedros 9y agoARM has a patent on AXI bus, but sure if it's expired, but whoever uses AXI with this CPU may need a license.
- Dolu 9y agoAre you sure it need a license ? I were thinking that AXI usage is royalities free (https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_A...)
- femto 9y agoIf there is a licensing problem with AXI, would Wishbone be a viable alternative [1]? [1] https://en.wikipedia.org/wiki/Wishbone_(computer_bus) https://en.wikipedia.org/wiki/Wishbone_(computer_bus)
- Dolu 9y agoYes it would be, it is very easy to retarget the CPU to another memory bus. Then the Wishbone one isn't "perfect" as it can't map memories which have latencies without performance penality. It would be oky for the data bus of the cpu with or without cache, but for the instruction, without instruction cache, peak CPI would be divided by the memory latency.
- bedros 9y agothat's my understanding from talking to an engineer at Qualcomm, however, if there's no need for a license, then it would make it lower cost to build SOC with off the shelf AXI IP
- femto 9y agoI've never understood why some people say a license is needed for something on which patents have expired. What's the legal basis, or is it bluff? I can understand that copyright exists in the documentation that describes AXI, but that copyright covers only their documentation and not your own implementation (or is some derivation claimed?). I can understand that trademark might exist in the name "AXI", so don't use that name. Trade secrets seem to be moot, if you're not associated with whoever is keeping the secret. If none of the above apply, what basis is there for demanding a license?