4 ms·

Seems kinda of silly, especially since PCI-Express is not cache coherent. Why not just connect high performance devices directly to hypertransport, Infinity fa

by sliken 9y ago

Seems kinda of silly, especially since PCI-Express is not cache coherent. Why not just connect high performance devices directly to hypertransport, Infinity fabric, QPI, or whatever the fast cache coherent serial interface of the day is?

hajile 9y ago
Because those aren't standard and nobody can agree on what the standard should be. Do you want to be the GPU manufacturer that has to make a half-dozen different kinds of the same card for different interfaces? What about the performance over distance? Most of that kind of bus is designed to work well over short distances and much stricter tolerances. These things would make cards cost many times more than they currently do which isn't feasible. Better a "slow" standard that works.
greglindahl 9y ago
The first generation of Infinipath did exactly that. We had to create a slot standard for Hypertransport (HTX), convince motherboard makers to build boards with that slot, and then at the end of the day we just ended up convincing everyone that they never wanted to go that route ever again. These days Intel's putting Omnipath on-package for Xeon Phi and Skylake. Likely it's still a PCI-Express connection, but it doesn't count against the total available lanes for external cards.
- jabl 9y ago
  > and then at the end of the day we just ended up convincing everyone that they never wanted to go that route ever again. Hmm, why? Intel executed well with Nehalem while AMD stumbled, leaving HTX even more niche than it already was, or do you mean there was some fundamental (technical) problem with it? > These days Intel's putting Omnipath on-package for Xeon Phi and Skylake. Likely it's still a PCI-Express connection, but it doesn't count against the total available lanes for external cards. Assuming the parts with integrated omni-path use the same socket, some pins will be needed for the OPA connection, no? Presumably pins that were reserved for PCIe in the normal chips, I'd guess...
  - greglindahl 9y ago
    Look at photos -- Omnipath Skylakes have an extra connector.
Unklejoe 9y ago
What exactly do you mean when you say PCI-Express isn't cache coherent? I would think that's dependent on the specific platform more than anything. For example, on a cache coherent architecture like the Freescale T2080, if a PCI device writes to some RAM location that's currently cached, the line automatically gets invalidated. There’s this whole “coherency fabric” thing which handles all of the snooping and interaction between the peripherals.

by sliken 9y ago

hajile 9y ago

Because those aren't standard and nobody can agree on what the standard should be. Do you want to be the GPU manufacturer that has to make a half-dozen different kinds of the same card for different interfaces? What about the performance over distance? Most of that kind of bus is designed to work well over short distances and much stricter tolerances. These things would make cards cost many times more than they currently do which isn't feasible. Better a "slow" standard that works.

greglindahl 9y ago

The first generation of Infinipath did exactly that. We had to create a slot standard for Hypertransport (HTX), convince motherboard makers to build boards with that slot, and then at the end of the day we just ended up convincing everyone that they never wanted to go that route ever again. These days Intel's putting Omnipath on-package for Xeon Phi and Skylake. Likely it's still a PCI-Express connection, but it doesn't count against the total available lanes for external cards.

jabl 9y ago
> and then at the end of the day we just ended up convincing everyone that they never wanted to go that route ever again. Hmm, why? Intel executed well with Nehalem while AMD stumbled, leaving HTX even more niche than it already was, or do you mean there was some fundamental (technical) problem with it? > These days Intel's putting Omnipath on-package for Xeon Phi and Skylake. Likely it's still a PCI-Express connection, but it doesn't count against the total available lanes for external cards. Assuming the parts with integrated omni-path use the same socket, some pins will be needed for the OPA connection, no? Presumably pins that were reserved for PCIe in the normal chips, I'd guess...
- greglindahl 9y ago
  Look at photos -- Omnipath Skylakes have an extra connector.

Unklejoe 9y ago

What exactly do you mean when you say PCI-Express isn't cache coherent? I would think that's dependent on the specific platform more than anything. For example, on a cache coherent architecture like the Freescale T2080, if a PCI device writes to some RAM location that's currently cached, the line automatically gets invalidated. There’s this whole “coherency fabric” thing which handles all of the snooping and interaction between the peripherals.