I'm curious to hear from AMD about the L3 cache latency issue. The article shows L3 access just a few ns quicker than going to DRAM, even to the other CCX on th

I'm curious to hear from AMD about the L3 cache latency issue. The article shows L3 access just a few ns quicker than going to DRAM, even to the other CCX on the same die. That's ugly! This strikes me as either a bug or a benchmarking glitch, though other benchmarks seem to imply that the situation is real. Assuming it's legit, this gives AMD a great opportunity for a boost in their first respin of the 8C/16T die.