>> Looking at the Skylake microarch, the instruction decode queue is 128 uOps thread, 2x64 uOps when threaded. No. Skylake does not have 128 μops with HT disab

>> Looking at the Skylake microarch, the instruction decode queue is 128 uOps thread, 2x64 uOps when threaded. No. Skylake does not have 128 μops with HT disabled. Skylake indeed was a big jump from Broadwell where the loopback buffer has 56 entries, 28 per hyperthread or 56 with HT off. Skylake has 64 μops per thread, HT on or off. 64 μops is a lot.