4 ms·

A comp.arch poster said: > The errata refers to the problem showing up on short loops of less than 64 instructions that use AH, BH, CH or DH. > Looking at th

A comp.arch poster said: > The errata refers to the problem showing up on short loops of less than 64 instructions that use AH, BH, CH or DH. > Looking at the Skylake microarch, the instruction decode queue is 128 uOps thread, 2*64 uOps when threaded. The Loop Stream Detector "can stream the same sequence of µOPs directly from the IDQ continuously without any additional fetching, decoding, or utilizing additional caches or resources." ... "capable of detecting loops up to 64 µOPs per thread". https://en.wikichip.org/wiki/intel/microarchitectures/skylake#.C2.B5OP-Fusion_.26_LSD https://en.wikichip.org/wiki/intel/microarchitectures/skylak... > So maybe the microcode update just shuts off the loopback detector. https://groups.google.com/d/msg/comp.arch/UkO4Z2FT18c/7YlC0aH7AQAJ https://groups.google.com/d/msg/comp.arch/UkO4Z2FT18c/7YlC0a... So if the bug is in the loop-detector, and the patch possibly disables it rather than fixes it, then does anyone have any before-and-after performance stats?

Tuna-Fish 9y ago
IIRC the Skylake loop buffer is not any faster than the uop cache, instead the reason for it's existence is to save power by not touching the cache. So you'd have to test power consumption instead?
CalChris 9y ago
>> Looking at the Skylake microarch, the instruction decode queue is 128 uOps thread, 2x64 uOps when threaded. No. Skylake does not have 128 μops with HT disabled. Skylake indeed was a big jump from Broadwell where the loopback buffer has 56 entries, 28 per hyperthread or 56 with HT off. Skylake has 64 μops per thread, HT on or off. 64 μops is a lot.