> Like where does the FPGA begin execution... When an FPGA powers up and self-configures, it's in an unknown state. If the design uses synchronous elements, th

> Like where does the FPGA begin execution... When an FPGA powers up and self-configures, it's in an unknown state. If the design uses synchronous elements, then reset logic must be architected in by the designer; in contrast, purely combinatorial circuits would not require reset logic since their outputs are not dependent on a clock edge.