8 ms·

Build your own FPGA (2012)

95 points by Cieplak 9y ago

mutagen 9y ago
With tongue firmly in cheek, I wonder how long before it becomes cost effective to mine Bitcoin with raw 74xx logic?
- nickpsecurity 9y ago
  Bitcoin miners are already using custom ASIC's on expensive, process nodes. Anyone using discrete logic would be running at a snail's pace compared to them.
  - tudorconstantin 9y ago
    What about mining ethereum on FPGA, would it be suited?
    - nickpsecurity 9y ago
      I don't know specifics on Ethereum. Basically, it has to be within the hardware constraints of FPGA's where CPU's, GPU's, and ASIC's don't convey an advantage.
  - hrac 9y ago
    Do you know how bitcoin miners use FPGAs? They're used for communication somehow. The Antminer S7 uses an SoC FPGA which allegedly was being used with ASICBoost.
    - nickpsecurity 9y ago
      You can implement many forms of I/O on FPGA's that let you bridge things that otherwise can't communicate for whatever reason. The FPGA can also be used to accelerate I/O vs a software implementation. For example, many network devices offload TCP/IP from the host. Finally, the connecting systems might have the necessary I/O built-in but FPGA accelerates some computational part of it. You see that in compression, TLS or IPsec engines. I don't know what Bitcoin people are doing. The above are common use cases, though.
- tonyarkles 9y ago
  http://www.potatosemi.com/potatosemi2010/products_74.html http://www.potatosemi.com/potatosemi2010/products_74.html You'll want fast 74-series logic!
- tyingq 9y ago
  That's (sort of) asked and answered in the comments :) "it would be theoretically possible. But if you calculate that... it isn't. For example: a DE0-Nano board ($79) mines at 12 MH/s. It has 22320 logic elements. Assuming the slices are equivalent, you would have to have 22320 of these boards. Each containing 12 7400 chips."
adrianratnapala 9y ago
One thing I've wondered is to what extent does discrete logic "scale proportionally" to integrated logic. I mean if you make a big machine out of these things, are the trade-offs you make regarding e.g. signal fanout and propagation delay similar to those made in an IC that did the same computation?
- NotQuantum 9y ago
  One of the biggest issues is complexity. Sure you can make some fairly complex things within an FPGA fabric, like a CPU or GPU. However, you'll see a slow down in two areas. The first is routing, whereas an IC would just have a wire between two components, FGPAs have to route further and through different interchanges. Second, components can only be built up through the basic components of the FGPA, typically a LUT and FFs. The more complex components, the more small parts. Another aspect is memory; blockram works decent but it's an explicit design choice, DRAM via DMA is also a pain too.
blackguardx 9y ago
This is really cool, but I'm surprised they didn't try to make a CPLD. You would at least have a shot at matching an IC for amount of logic gates.
- arjo1 9y ago
  Out of curiosity what makes an CPLD different from an FPGA?
  - kevin_thibedeau 9y ago
    Originally CPLDs used arrays of PLDs/PLAs which use a wide network of programmable AND-OR gates to implement logic equations with relatively sparse routing resources between logic elements. FPGAs will use a more fine grained element for implementing logic (SRAM LUTs or small clusters of muxes) with denser routing resources. That distinction is a bit blurred nowadays because Altera has "CPLD" products that are using conventional FPGA architecture equivalent to what was state of the art for FPGAs 25 years ago.
  - blackguardx 9y ago
    It is mainly an architecture difference. An FPGA is typically made up of many logic blocks that contain a programmable look up table (LUT) connected to a flip flop. There are also various multiplexers (muxes) that route signals around the flip-flop or to other neighboring logic blocks. In this way, you can chain many of these logic blocks together to create your desired circuit. A CPLD typically has a network of And or Or gates leading to the pins of the device. The outputs of these gates then feed into the complementary gate (Or for And and And for Or) and then most likely into flip flops. You program the device by selectively connecting the pins through a switching matrix to the various elements of the first logic array and then another switching matrix to the various elements of the second logic array. There is also the possibility for a third switching matrix for feedback through the system.
  - hervature 9y ago
    As the others have pointed out the technical details, the high level difference is that FPGA's are typically volatile and hence lose their programing once there is a power loss. CPLD's have non-volatile memory that allow for hard reseting and so are used in environments that need fault tolerance (factories, airplanes, etc.).
kenjackson 9y ago
Is there a good idiots guide to understanding FPGAs and how to develop for them? I have a CS background (so I've read both Hennessy & Paterson books) but don't know FPGAs nor have an EE background. Reading about FPGAs always confuses me, from the perspective of someone who thinks as a normal SW developer. Like where does the FPGA begin execution, etc... TIA
- frahs 9y ago
  FPGA's don't have a runtime or execution. Think of an FPGA like a bunch of logic gates you connect. If you have further questions I can try to answer them.
- gricardo99 9y ago
  FPGAs are synchronous digital logic. That may sound complicated but it's actually conceptually quite simple. If I had a white board I could show you a diagram in 10 seconds that would probably clear everything up. But instead here's my attempt at a description. 1- digital logic. From your CS background you're familiar with AND, OR, NOT, etc... imagine having a bunch of these simple functions and being able to combine them and reorganize them to meet your needs. These functions are "continuous " in that they always update their output when their inputs change. 2 - synchronous: this essentially means "registers" that store values (flip flops) are controlled by a global clock signal. When the clock "triggers" (usually on the rising or falling edge) new values are loaded into the registers. So with those definitions in mind, an FPGA, or any other synchronous digital system, can be thought of as: inputs feeding registers, feeding a cloud of logic, feeding registers, etc... for as many stages as is needed (or possible) until you get to the outputs. Edits: clarifications (hopefully)
  - DigitalJack 9y ago
    That's actually a pretty good overview with an appropriate level of simplifying. I don't see that much here with regards to digital logic.
- metaphor 9y ago
  > Like where does the FPGA begin execution... When an FPGA powers up and self-configures, it's in an unknown state. If the design uses synchronous elements, then reset logic must be architected in by the designer; in contrast, purely combinatorial circuits would not require reset logic since their outputs are not dependent on a clock edge.
zw123456 9y ago
Funny, just the other day at work I was trying to explain to someone what an FPGA was and I used the 7400 TLL example and said imagine if you had a crate full of TTL chips and you could put them all onto a single die, arrange them with the most common ones in little module called LUT's and then be able to cross connect any input to any output using a memory type array. The guy I was explaining it to was familiar with TTL from school and immediately the light went on.

95 points by Cieplak 9y ago

mutagen 9y ago

With tongue firmly in cheek, I wonder how long before it becomes cost effective to mine Bitcoin with raw 74xx logic?

nickpsecurity 9y ago
Bitcoin miners are already using custom ASIC's on expensive, process nodes. Anyone using discrete logic would be running at a snail's pace compared to them.
- tudorconstantin 9y ago
  What about mining ethereum on FPGA, would it be suited?
  - nickpsecurity 9y ago
    I don't know specifics on Ethereum. Basically, it has to be within the hardware constraints of FPGA's where CPU's, GPU's, and ASIC's don't convey an advantage.
- hrac 9y ago
  Do you know how bitcoin miners use FPGAs? They're used for communication somehow. The Antminer S7 uses an SoC FPGA which allegedly was being used with ASICBoost.
  - nickpsecurity 9y ago
    You can implement many forms of I/O on FPGA's that let you bridge things that otherwise can't communicate for whatever reason. The FPGA can also be used to accelerate I/O vs a software implementation. For example, many network devices offload TCP/IP from the host. Finally, the connecting systems might have the necessary I/O built-in but FPGA accelerates some computational part of it. You see that in compression, TLS or IPsec engines. I don't know what Bitcoin people are doing. The above are common use cases, though.
tonyarkles 9y ago
http://www.potatosemi.com/potatosemi2010/products_74.html http://www.potatosemi.com/potatosemi2010/products_74.html You'll want fast 74-series logic!
tyingq 9y ago
That's (sort of) asked and answered in the comments :) "it would be theoretically possible. But if you calculate that... it isn't. For example: a DE0-Nano board ($79) mines at 12 MH/s. It has 22320 logic elements. Assuming the slices are equivalent, you would have to have 22320 of these boards. Each containing 12 7400 chips."

adrianratnapala 9y ago

One thing I've wondered is to what extent does discrete logic "scale proportionally" to integrated logic. I mean if you make a big machine out of these things, are the trade-offs you make regarding e.g. signal fanout and propagation delay similar to those made in an IC that did the same computation?

NotQuantum 9y ago
One of the biggest issues is complexity. Sure you can make some fairly complex things within an FPGA fabric, like a CPU or GPU. However, you'll see a slow down in two areas. The first is routing, whereas an IC would just have a wire between two components, FGPAs have to route further and through different interchanges. Second, components can only be built up through the basic components of the FGPA, typically a LUT and FFs. The more complex components, the more small parts. Another aspect is memory; blockram works decent but it's an explicit design choice, DRAM via DMA is also a pain too.

blackguardx 9y ago

This is really cool, but I'm surprised they didn't try to make a CPLD. You would at least have a shot at matching an IC for amount of logic gates.

arjo1 9y ago
Out of curiosity what makes an CPLD different from an FPGA?
- kevin_thibedeau 9y ago
  Originally CPLDs used arrays of PLDs/PLAs which use a wide network of programmable AND-OR gates to implement logic equations with relatively sparse routing resources between logic elements. FPGAs will use a more fine grained element for implementing logic (SRAM LUTs or small clusters of muxes) with denser routing resources. That distinction is a bit blurred nowadays because Altera has "CPLD" products that are using conventional FPGA architecture equivalent to what was state of the art for FPGAs 25 years ago.
- blackguardx 9y ago
  It is mainly an architecture difference. An FPGA is typically made up of many logic blocks that contain a programmable look up table (LUT) connected to a flip flop. There are also various multiplexers (muxes) that route signals around the flip-flop or to other neighboring logic blocks. In this way, you can chain many of these logic blocks together to create your desired circuit. A CPLD typically has a network of And or Or gates leading to the pins of the device. The outputs of these gates then feed into the complementary gate (Or for And and And for Or) and then most likely into flip flops. You program the device by selectively connecting the pins through a switching matrix to the various elements of the first logic array and then another switching matrix to the various elements of the second logic array. There is also the possibility for a third switching matrix for feedback through the system.
- hervature 9y ago
  As the others have pointed out the technical details, the high level difference is that FPGA's are typically volatile and hence lose their programing once there is a power loss. CPLD's have non-volatile memory that allow for hard reseting and so are used in environments that need fault tolerance (factories, airplanes, etc.).

kenjackson 9y ago

Is there a good idiots guide to understanding FPGAs and how to develop for them? I have a CS background (so I've read both Hennessy & Paterson books) but don't know FPGAs nor have an EE background. Reading about FPGAs always confuses me, from the perspective of someone who thinks as a normal SW developer. Like where does the FPGA begin execution, etc... TIA

frahs 9y ago
FPGA's don't have a runtime or execution. Think of an FPGA like a bunch of logic gates you connect. If you have further questions I can try to answer them.
gricardo99 9y ago
FPGAs are synchronous digital logic. That may sound complicated but it's actually conceptually quite simple. If I had a white board I could show you a diagram in 10 seconds that would probably clear everything up. But instead here's my attempt at a description. 1- digital logic. From your CS background you're familiar with AND, OR, NOT, etc... imagine having a bunch of these simple functions and being able to combine them and reorganize them to meet your needs. These functions are "continuous " in that they always update their output when their inputs change. 2 - synchronous: this essentially means "registers" that store values (flip flops) are controlled by a global clock signal. When the clock "triggers" (usually on the rising or falling edge) new values are loaded into the registers. So with those definitions in mind, an FPGA, or any other synchronous digital system, can be thought of as: inputs feeding registers, feeding a cloud of logic, feeding registers, etc... for as many stages as is needed (or possible) until you get to the outputs. Edits: clarifications (hopefully)
- DigitalJack 9y ago
  That's actually a pretty good overview with an appropriate level of simplifying. I don't see that much here with regards to digital logic.
metaphor 9y ago
> Like where does the FPGA begin execution... When an FPGA powers up and self-configures, it's in an unknown state. If the design uses synchronous elements, then reset logic must be architected in by the designer; in contrast, purely combinatorial circuits would not require reset logic since their outputs are not dependent on a clock edge.

zw123456 9y ago

Funny, just the other day at work I was trying to explain to someone what an FPGA was and I used the 7400 TLL example and said imagine if you had a crate full of TTL chips and you could put them all onto a single die, arrange them with the most common ones in little module called LUT's and then be able to cross connect any input to any output using a memory type array. The guy I was explaining it to was familiar with TTL from school and immediately the light went on.