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There are simple open source cores for quite a few IO standards. Some ARM SoCs use Cadence or Synopsys cores. What could be a good advert for RISC-V would be t
by rjsw 9y ago
There are simple open source cores for quite a few IO standards. Some ARM SoCs use Cadence or Synopsys cores.
What could be a good advert for RISC-V would be to design a SoC that used a full featured RV64 main core and simpler RV32I cores as offload engines for each IO device.
- tyingq 9y agoThe lowrisc project has something like that. They call them minion cores. http://www.lowrisc.org/docs/memo-2014-001-tagged-memory-and-minion-cores/ http://www.lowrisc.org/docs/memo-2014-001-tagged-memory-and-...