4 ms·
Kind of a performance limiter if you actually do it. There are architectures where the programmers' reference manual is written as if registers are in main mem
by dbcurtis 9y ago
Kind of a performance limiter if you actually do it. There are architectures where the programmers' reference manual is written as if registers are in main memory, but the CPU brings the active registers into physical registers and fakes it. In olden days (of water chillers) I worked on CPU's like that. It essentially requires creating a look-aside buffer so that memory addresses that map to registers in the current context get redirected to the physical registers, and you have to watch out for order dependencies.
So not totally crazy, but a severe performance limiter unless you can afford the complexity of the standard trickery.
TI did make a personal computer that competed with the likes of the VIC-20. It was sloooooow, but had nice (for the time) color graphics.
(edit typos)
- mjevans 9y agoWhen I was in college an 6800 derived embedded systems prototype board had 'really fast' in-package memory used for such a setup. In the context of something vaguely like an SoC where you can make "0 page" memory registers fast with a small bank of high speed SRAM it can make sense, particularly for decoupling manufacturing defects or silicon production processes. Of course for modern, potentially out of order and speculative branch predicting, pipelined instruction systems this is a horrid idea.
- dbcurtis 9y agoWell, actually, once you buy into everything you need for O-O-O execution with synchronous exceptions, a lot of stuff that seems difficult at first glance becomes cheap because you can build on the existing O-O-O infrastructure. Anytime you can belly-flop onto the reorder buffer scoreboard the hard stuff just falls out.
- deepnotderp 9y agoDamn, and I thought x86 was a bad architectural decision....