3 ms·
Did they just beat Intel? http://www.anandtech.com/show/11112/intel-to-equip-fab-42-for-7-nm http://www.anandtech.com/show/11112/intel-to-equip-fab-42-fo...
by smilekzs 9y ago
Did they just beat Intel?
http://www.anandtech.com/show/11112/intel-to-equip-fab-42-for-7-nm http://www.anandtech.com/show/11112/intel-to-equip-fab-42-fo...
- Armisael16 9y agoYou can't compare numbers across fabs anymore. Die size is basically marketing at this point.
- mtgx 9y agoThey seem to have beaten Intel in adopting EUV lithography at least. IBM's 5nm gate-all-around FET (GAAFET) process, which GloFlo should be able have ready for production in 2020, also looks very interesting. https://www-03.ibm.com/press/us/en/pressrelease/52531.wss https://www-03.ibm.com/press/us/en/pressrelease/52531.wss
- deepnotderp 9y agoThey're only using EUV for a, couple of layers. Intel is using SADP (or SAQP), that should be able to hold its own.
- sbierwagen 9y agoDie size Feature size?
- Armisael16 9y agoYep. My bad.
- virtuallynathan 9y agoNot so far as I know. Intel is suggesting people measure in million transistors per square millimeter, MTr/mm^2. GloFlo 7nm is at ~17MTr/mm^2 Intel 14nm is at ~37.5MTr/mm^2 Intel 10nm claims to be ~100MTr/mm^2 These are now "14nm class", "10nm class", etc... the number no long really relates to a meaningful feature size, as I understand it.