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GlobalFoundries Details 7 nm Plans: Three Generations, 700 mm², HVM in 2018
- smilekzs 9y agoDid they just beat Intel? http://www.anandtech.com/show/11112/intel-to-equip-fab-42-for-7-nm http://www.anandtech.com/show/11112/intel-to-equip-fab-42-fo...
- Armisael16 9y agoYou can't compare numbers across fabs anymore. Die size is basically marketing at this point.
- mtgx 9y agoThey seem to have beaten Intel in adopting EUV lithography at least. IBM's 5nm gate-all-around FET (GAAFET) process, which GloFlo should be able have ready for production in 2020, also looks very interesting. https://www-03.ibm.com/press/us/en/pressrelease/52531.wss https://www-03.ibm.com/press/us/en/pressrelease/52531.wss
- deepnotderp 9y agoThey're only using EUV for a, couple of layers. Intel is using SADP (or SAQP), that should be able to hold its own.
- sbierwagen 9y agoDie size Feature size?
- Armisael16 9y agoYep. My bad.
- virtuallynathan 9y agoNot so far as I know. Intel is suggesting people measure in million transistors per square millimeter, MTr/mm^2. GloFlo 7nm is at ~17MTr/mm^2 Intel 14nm is at ~37.5MTr/mm^2 Intel 10nm claims to be ~100MTr/mm^2 These are now "14nm class", "10nm class", etc... the number no long really relates to a meaningful feature size, as I understand it.
- deepnotderp 9y agoInteresting, I wonder if the reticle limit is smaller on EUV litho machines, that would explain their smaller maximum die size compared to 193i immersion steppers.
- sliverstorm 9y agoNot knowing for sure, I'd wonder if it's limited by EUV power output. The main challenge has always been, how to produce enough light. Whereas with regular litho, your reticle limit is a function of how expensive the lens is.
- deepnotderp 9y agoDefinitely, I think this is the issue. You're definitely right that the problem with EUV is how to get a strong enough power source.
- SemiTom 9y agoInterview with GF CTO here https://semiengineering.com/inside-fd-soi-scaling/ https://semiengineering.com/inside-fd-soi-scaling/
- leggomylibro 9y agoSeeing these advances in feature size always makes me wonder: is there a guide anywhere for making your own, maybe mm-scale, dies? Would the physics work at that large scale? It could be a cool way to demonstrate the concepts. Like, you can make your own capacitors by rolling up two interleaved sheets of baking paper and aluminum foil. Because of the large scale of the gap between the conductive layers, you'll have trouble breaking a few nF of capacitance. It will likely withstand tens of kilovolts, however, because the parchment barrier is thick and hardy compared to what is used in your average electrolytic capacitor.
- tachyonbeam 9y agoI think that making semiconductors is unfortunately out of the reach of hobbyists. You'd have to grow purified crystals (or buy them), slice and polish them, etc. The various processes needed for lithography involve toxic chemicals too AFAIK. That being said, if you want to make your own large-scale CPU, you can still build one out of discrete 74-series logic, individual transistors, or relays. Takes a lot of dedication, but that is entirely within your reach. A fun example of a CPU built with discrete SMD transistors, the monster 6502 https://www.youtube.com/watch?v=tQIwS2GzXLI https://www.youtube.com/watch?v=tQIwS2GzXLI There's also the MegaProcessor: https://www.youtube.com/watch?v=lNa9bQRPMB8 https://www.youtube.com/watch?v=lNa9bQRPMB8 Zusie relay computer: https://www.youtube.com/watch?v=NXeBR-lbnjI https://www.youtube.com/watch?v=NXeBR-lbnjI
- frozenport 9y agoOr you can make it in HDL and pay somebody to fab it
- chocolatebunny 9y agoSo what's the cheapest fab in the world? Maybe I should just stick with FPGAs.
- sbierwagen 9y ago
- azinman2 9y agoThinking about the recent HN link to the article about the toxicity of photoresisters. Would love to know the environmental / workplace toxicity ramifications (or if it’s just business as usual...)
- jacquesm 9y agoYou can look those up easily enough: http://www.msds.com/ http://www.msds.com/