5 ms·

L3 is a victim cache? Intels L4 is the victim cache for their inclusive L3. How does that work? And their L2 is basically a buffer between their L1 and L3. Tha

L3 is a victim cache? Intels L4 is the victim cache for their inclusive L3. How does that work? And their L2 is basically a buffer between their L1 and L3. That doesnt make sense to me. I can't find any good info on this.

IanCutress 9y ago
Check AnandTech's Zen review and their recent Skylake-X review for the latest details.