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Is L2 shared on AMD or are they going the Intel route and making it per core? Is there any info on cache architecture for Zen?
by jnordwick 9y ago
Is L2 shared on AMD or are they going the Intel route and making it per core?
Is there any info on cache architecture for Zen?
- dom0 9y agoHm? L2 is per core. Always has been in a three+ layer architecture. Zen has 512K L2 per core and 8M L3 per CCX (two CCX per dice). L3 is a victim cache iirc, unlike previous generations where the L3 was inclusive. Intel usually went with a similar scheme in the last few years, where the L3 is partitioned into slices assigned to cores; accessing the local slice is faster than a non-local slice. Skylake-SP deviates from this (significantly), for better ... or worse.
- jnordwick 9y agoL3 is a victim cache? Intels L4 is the victim cache for their inclusive L3. How does that work? And their L2 is basically a buffer between their L1 and L3. That doesnt make sense to me. I can't find any good info on this.
- IanCutress 9y agoCheck AnandTech's Zen review and their recent Skylake-X review for the latest details.
- snovv_crash 9y agoSorry, I meant L3 without leaving the CCX.