You are probably mixing RTL design with Place and Route, those are two completely different things. You can design and simulate without your FPGA, most of the

You are probably mixing RTL design with Place and Route, those are two completely different things. You can design and simulate without your FPGA, most of the tools allow for simulation without calling a GUI. It will be not different than calling GCC. Worst case scenario, you can always use this open source Verilog simulator, it's good enough if you are only designing for FPGAs: http://iverilog.icarus.com/ http://iverilog.icarus.com/ Again, you don't need any FPGA to do the design and you shouldn't even use it, it's a waste of time synthesizing the design every time you make a change. Place and Route comes after the design gets to a complete state and you should only be able to do it once. If you are doing something different from this flow, you are most likely doing it wrong.