The synthesis tools even try wery hard to optimize dumb registers away from your design (you typically blow away ~40 gate equivalents for one bit of simple memo

The synthesis tools even try wery hard to optimize dumb registers away from your design (you typically blow away ~40 gate equivalents for one bit of simple memory implemented by logic cell). While having clock-gated registers makes the design harder to understand and thus is undesirable, another reason why it is undesirable is that it tends to break any such optimizations performed by synthesis toolchain.