4 ms·
8 DDR channels. Seems like everyone putting 30+ cores on a chip needs to learn this lesson. Memory bandwidth is the bottleneck. Intel uses HBM stacked on the Xe
by m-j-fox 9y ago
8 DDR channels. Seems like everyone putting 30+ cores on a chip needs to learn this lesson. Memory bandwidth is the bottleneck. Intel uses HBM stacked on the Xeon Phi. Anyone who has the capability should do likewise or maybe try 8 DDR channels, pin count be damned.
- awordnot 9y agoThis is what AMD's new Epyc server CPUs are rumored to have.
- sliken 9y agoQuite more than a rumor at this point. The Eypc has 4 Ryzen dies, each of which on an on chip 2 channel memory controller. http://www.amd.com/en-us/press-releases/Pages/amd-raises-expectations-2017may16.aspx http://www.amd.com/en-us/press-releases/Pages/amd-raises-exp...