3 ms·
My understanding is that AMD probably originally designed SYSRET assuming that SS contained the correct values already (except SS.DPL of course, which I guess i
by yuhong 9y ago
My understanding is that AMD probably originally designed SYSRET assuming that SS contained the correct values already (except SS.DPL of course, which I guess is where the stuff where they set it to RPL comes from). When they designed x86-64 however, they decided to set SS to null selectors in interrupts. Of course, these values are normally ignored in 64-bit long mode. Long mode is also when they fixed SYSCALL/SYSRET by adding an option to mask EFLAGS (and store the old value in R11): http://web.archive.org/web/20120813101603/http://www.x86-64.org:80/pipermail/discuss/2000-October/001019.html http://web.archive.org/web/20120813101603/http://www.x86-64....
- yuhong 9y agoBTW, SYSENTER/SYSEXIT was designed by Andy Glew, which mentioned in https://groups.google.com/d/msg/comp.arch/Bf-4VflljF4/4hNvyrHN8pAJ https://groups.google.com/d/msg/comp.arch/Bf-4VflljF4/4hNvyr... that "(I wanted to avoid changing SS:ESP, so that it could be just a single register write if CS:EIP were co-renamed, but microcode thought that would violate invariants about SS RPL they wanted to maintain." I wonder if part of the problem is that AMD was still new to x86 CPU design back when SYSCALL/SYSRET was developed as part of the K6.