People frequently complain about the complexity of decoding the x86 ISA and that seems to be what you're arguing against. But I didn't see the OP as making tha

People frequently complain about the complexity of decoding the x86 ISA and that seems to be what you're arguing against. But I didn't see the OP as making that argument at all. Instead it's things like the way x86 handles integer condition codes that has a huge effect on the complexity of the reorder buffer because now you have to track this additional input for each of your instructions. But quite apart from the transistor cost of various legacy feature is the engineering cost. When designing a new x86 chip you have to make sure that every instruction works correctly in every mode that supports it and that's hard. NRE is a large fraction of the cost of each chip and verification is a big part of that. Intel had all the transistors in place to support SMT early on in the Pentium IV development but they didn't turn it on until Northwood because it was hard for them to make sure it worked reliably. And recently look at the problems Intel has been having getting TSX to work right or the problems AMD had with legacy modes in Ryzen. And also, decode might not take very many transistors but those transistors are in constant use and consume way more power than the huge seas of 8T SRAM cells in the local cache despite being hugely outnumbered. This is far from the majority of the chip's power but every little bit counts.