>Readability. Just like you can cram a whole bunch of code on a single line for a regular program it doesn't help a person trying to understand the code. Langu

>Readability. Just like you can cram a whole bunch of code on a single line for a regular program it doesn't help a person trying to understand the code. Language syntax is also a major problem. For example, if the author chose to join those two always statements he/she would have to use begin/end keywords which are ugly and cause visual "clutter". VHDL is not better in that regard, I'd say it's even worse (e.g. converting back and forth between std_logic_vector and signed/unsigned). The only drawback I see in the author's code is that using (lots of) multiple always blocks may slow down simulation, but that's a fair price to pay if the code is more readable