3 ms·
Well (from a VERY VERY small sample) I think yes (I was referring more generally to people doing logic design in Verilog, not just FPGAs) - in my experience the
by Taniwha 9y ago
Well (from a VERY VERY small sample) I think yes (I was referring more generally to people doing logic design in Verilog, not just FPGAs) - in my experience they tended to write at a higher level and knock out gates faster .... that left them with more time to optimise their designs
But this is old data - the world changes
- jnordwick 9y agoIn my experience although limited most software developers write terrible HDL code. They think too serially, step wise, and aren't very good at parallelizing their code on the level necessary for good hardware design. The exception to this are those with good hardware sympathy. They can after carry over that detail oriented thought process.
- Taniwha 9y agoMaybe, but I'm not talking about beginners here, I'm talking about people who already have years of experience