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> In Chisel, you write Scala that is compiled to Verilog(?) Berkeley grad student here. The current Chisel compiler generates an intermediate representation th
by zhemao 9y ago
> In Chisel, you write Scala that is compiled to Verilog(?)
Berkeley grad student here. The current Chisel compiler generates an intermediate representation that can be compiled to any target. Our Verilog backend is definitely the most developed, but we also have an interpreter that can directly simulate the IR.
- aseipp 9y agoThanks! Is this a reference to FIRRTL that I've seen some light references to (e.g. Yosys's experimental FIRRTL backend)? I was under the impression FIR was somewhat new and wasn't sure if it was used in Chisel (yet). (To be clear, I figured you compiled to a generic IR before lowering onto some chosen HDL, regardless if it's FIR or not, but wasn't sure if Chisel had multiple HDL backends strictly speaking).
- zhemao 9y agoYes, I'm talking about FIRRTL, which is used in the latest version of Chisel (Chisel 3). There aren't official releases of this version yet, but you can get snapshots (if you don't mind some API breakage now and then). It works fairly well now and we use it in all our RTL designs.