3 ms·Why not target verilog directly? Chisel is just a verilog generator in the end.by hobo_mark 9y agoWhy not target verilog directly? Chisel is just a verilog generator in the end.vasilia 9y agoBecause of ML and neural networks hype. No one wants to learn VDHL or Verilog, they want OpenCL or something similar.alunaryak 9y agoI hear what you're saying, but Chisel is a lot closer to an RTL like Verilog than it is to OpenCL.deleted 9y ago[deleted]