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We are not only concerned by FPGA but also CGRA (developping our own: Plasticine). For FPGA, we target Chisel. Chisel is Verilog without the boilerplate. We aim
by rubenfiszel 9y ago
We are not only concerned by FPGA but also CGRA (developping our own: Plasticine). For FPGA, we target Chisel. Chisel is Verilog without the boilerplate. We aim to be more high-level by generating also all the control flow.
- eeks 9y agoIntuitively it seems easier to build strong inference heuristics for CGRA than FPGA given the more constrained (limited?) degrees of design freedom. I've always been wary of inference-based systems that target clocked logic. Most of them (especially the C-based ones) are not suited to produce efficient designs and usually require some heavy massaging of the original code to make the inference system happy.
- petra 9y agoLike with any academic work, the biggest challenge is a route to market. Do you plan on any(for the your hardware tech) ?
- pawadu 9y agoI think the main challenge of Chisel is the choice of language (Scala). The designers of Chisel don't speak the same "language" as your average hardware designer. Maybe this is why people have invested tons of hours to re-write risc-v in pure verilog [1] and VHDL [2]. --- [1] https://github.com/cliffordwolf/picorv32 https://github.com/cliffordwolf/picorv32 [2] https://github.com/sergeykhbr/riscv_vhdl https://github.com/sergeykhbr/riscv_vhdl