5 ms·

I'll RTFM later, but in the meantime : how to you compare to Chisel https://chisel.eecs.berkeley.edu https://chisel.eecs.berkeley.edu ?

by eeks 9y ago

aseipp 9y ago
Spatial is built on Chisel, and from what I can tell, basically offers you an "SDSoC" experience for Scala. In Chisel, you write Scala that is compiled to Verilog(?) and you put it into your synthesis toolchain. But Chisel is mostly just that: it's a HDL, and not much more. And if you want to talk to an FPGA, especially from software, you still have to write another pile of glue that does interfacing to your device, over your peripherials, etc. Spatial gives you more on top of Chisel. Instead, you simply write a single program and say "Accelerate this bit", and it generates both the hardware and software and glues it all together. This means you write a single program once and the compiler generates all the glue for you, so the usage is more seamless. This is what "SDSoC" from Xilinx does, but for C/C++. You simply write a C program and annotate functions as "Accelerate" and it compiles both the hardware and software for you and generates the interconnections. Spatial is like that, for Scala.
- rubenfiszel 9y ago
  Our project is Spatial, not Spinal though :)
  - aseipp 9y ago
    Sorry about that, fixed! I get confused, I use Clash/Haskell more than Scala, so this is all second hand :) (IIRC, Spinal is a Chisel fork which is probably where it came from...)
- eeks 9y ago
  Gotcha. So very similar to what IBM tried to do with LiquidMetal (http://researcher.watson.ibm.com/researcher/view_group.php?id=122 http://researcher.watson.ibm.com/researcher/view_group.php?i...), albeit for Java.
- zhemao 9y ago
  > In Chisel, you write Scala that is compiled to Verilog(?) Berkeley grad student here. The current Chisel compiler generates an intermediate representation that can be compiled to any target. Our Verilog backend is definitely the most developed, but we also have an interpreter that can directly simulate the IR.
  - aseipp 9y ago
    Thanks! Is this a reference to FIRRTL that I've seen some light references to (e.g. Yosys's experimental FIRRTL backend)? I was under the impression FIR was somewhat new and wasn't sure if it was used in Chisel (yet). (To be clear, I figured you compiled to a generic IR before lowering onto some chosen HDL, regardless if it's FIR or not, but wasn't sure if Chisel had multiple HDL backends strictly speaking).
    - zhemao 9y ago
      Yes, I'm talking about FIRRTL, which is used in the latest version of Chisel (Chisel 3). There aren't official releases of this version yet, but you can get snapshots (if you don't mind some API breakage now and then). It works fairly well now and we use it in all our RTL designs.
rubenfiszel 9y ago
We are not only concerned by FPGA but also CGRA (developping our own: Plasticine). For FPGA, we target Chisel. Chisel is Verilog without the boilerplate. We aim to be more high-level by generating also all the control flow.
- eeks 9y ago
  Intuitively it seems easier to build strong inference heuristics for CGRA than FPGA given the more constrained (limited?) degrees of design freedom. I've always been wary of inference-based systems that target clocked logic. Most of them (especially the C-based ones) are not suited to produce efficient designs and usually require some heavy massaging of the original code to make the inference system happy.
- petra 9y ago
  Like with any academic work, the biggest challenge is a route to market. Do you plan on any(for the your hardware tech) ?
  - pawadu 9y ago
    I think the main challenge of Chisel is the choice of language (Scala). The designers of Chisel don't speak the same "language" as your average hardware designer. Maybe this is why people have invested tons of hours to re-write risc-v in pure verilog [1] and VHDL [2]. --- [1] https://github.com/cliffordwolf/picorv32 https://github.com/cliffordwolf/picorv32 [2] https://github.com/sergeykhbr/riscv_vhdl https://github.com/sergeykhbr/riscv_vhdl

I'll RTFM later, but in the meantime : how to you compare to Chisel https://chisel.eecs.berkeley.edu https://chisel.eecs.berkeley.edu ?

by eeks 9y ago

I'll RTFM later, but in the meantime : how to you compare to Chisel https://chisel.eecs.berkeley.edu https://chisel.eecs.berkeley.edu ?

aseipp 9y ago

Spatial is built on Chisel, and from what I can tell, basically offers you an "SDSoC" experience for Scala. In Chisel, you write Scala that is compiled to Verilog(?) and you put it into your synthesis toolchain. But Chisel is mostly just that: it's a HDL, and not much more. And if you want to talk to an FPGA, especially from software, you still have to write another pile of glue that does interfacing to your device, over your peripherials, etc. Spatial gives you more on top of Chisel. Instead, you simply write a single program and say "Accelerate this bit", and it generates both the hardware and software and glues it all together. This means you write a single program once and the compiler generates all the glue for you, so the usage is more seamless. This is what "SDSoC" from Xilinx does, but for C/C++. You simply write a C program and annotate functions as "Accelerate" and it compiles both the hardware and software for you and generates the interconnections. Spatial is like that, for Scala.

rubenfiszel 9y ago
Our project is Spatial, not Spinal though :)
- aseipp 9y ago
  Sorry about that, fixed! I get confused, I use Clash/Haskell more than Scala, so this is all second hand :) (IIRC, Spinal is a Chisel fork which is probably where it came from...)
eeks 9y ago
Gotcha. So very similar to what IBM tried to do with LiquidMetal (http://researcher.watson.ibm.com/researcher/view_group.php?id=122 http://researcher.watson.ibm.com/researcher/view_group.php?i...), albeit for Java.
zhemao 9y ago
> In Chisel, you write Scala that is compiled to Verilog(?) Berkeley grad student here. The current Chisel compiler generates an intermediate representation that can be compiled to any target. Our Verilog backend is definitely the most developed, but we also have an interpreter that can directly simulate the IR.
- aseipp 9y ago
  Thanks! Is this a reference to FIRRTL that I've seen some light references to (e.g. Yosys's experimental FIRRTL backend)? I was under the impression FIR was somewhat new and wasn't sure if it was used in Chisel (yet). (To be clear, I figured you compiled to a generic IR before lowering onto some chosen HDL, regardless if it's FIR or not, but wasn't sure if Chisel had multiple HDL backends strictly speaking).
  - zhemao 9y ago
    Yes, I'm talking about FIRRTL, which is used in the latest version of Chisel (Chisel 3). There aren't official releases of this version yet, but you can get snapshots (if you don't mind some API breakage now and then). It works fairly well now and we use it in all our RTL designs.

rubenfiszel 9y ago

We are not only concerned by FPGA but also CGRA (developping our own: Plasticine). For FPGA, we target Chisel. Chisel is Verilog without the boilerplate. We aim to be more high-level by generating also all the control flow.

eeks 9y ago
Intuitively it seems easier to build strong inference heuristics for CGRA than FPGA given the more constrained (limited?) degrees of design freedom. I've always been wary of inference-based systems that target clocked logic. Most of them (especially the C-based ones) are not suited to produce efficient designs and usually require some heavy massaging of the original code to make the inference system happy.
petra 9y ago
Like with any academic work, the biggest challenge is a route to market. Do you plan on any(for the your hardware tech) ?
- pawadu 9y ago
  I think the main challenge of Chisel is the choice of language (Scala). The designers of Chisel don't speak the same "language" as your average hardware designer. Maybe this is why people have invested tons of hours to re-write risc-v in pure verilog [1] and VHDL [2]. --- [1] https://github.com/cliffordwolf/picorv32 https://github.com/cliffordwolf/picorv32 [2] https://github.com/sergeykhbr/riscv_vhdl https://github.com/sergeykhbr/riscv_vhdl