There are some interesting open CPU designs at the high level, but it is basically impossible to fab a state of the art chip with truly open designs. From the s

There are some interesting open CPU designs at the high level, but it is basically impossible to fab a state of the art chip with truly open designs. From the standard cells down, you are unlikely to be allowed to know anything. Bunnie Huang touched on this, and other themes, at the 6th workshop (though sadly the audio was not captured directly from the microphone, so it's crummy PA sound from the perspective of the camera): https://www.youtube.com/watch?v=zXwy65d_tu8 https://www.youtube.com/watch?v=zXwy65d_tu8 That said, if you mean the high level/functional design of the chip, then there are quite a few open ones. Chris Celio is working on a (seemingly quite excellent) superscalar out of order RISC-V called BooM. There's a reference in-order core called Rocket, which is attacked to a lot of "uncore" infrastructure which is reused by BooM and a couple other chips. They also have an introductory educational RISC-V core called Sodor. There's Z-scale which is a deeply-embedded-sized in-order core. Clifford Wolf, in addition to developing a formal verification framework for RISC-V cores, has a small RISC-V core called PicoRV32. SiFive's FE310 is open to the extent permitted by the agreements they've had to make to fab the chips, which includes RTL for the core itself and a couple other things. FE310 being the model they shipped in their Arduino-compatible HiFive1 boards.