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Ok, so the ISA is open. What about the rest of the design of the CPU?

by ant6n 9y ago

ktta 9y ago
BSD license means that any company which uses this ISA doesn't have to. So you won't be seeing any completely open GPUs or CPUs by Nvidia or AMD. That's because the architecture is a huge part of where the work goes into. All this project is trying to do is to democratize the ISA. Which means, once the big companies start using this ISA, the ISA will get popular. Then a small company can release a niche chip and not have to pay anything. Examples: Microsoft Hololens uses Xtensa architecture - which is expensive and the support is apparently terrible. Nvidia's Tegra chip uses ARM's ISA and makes it's own modifications, but still has to pay a LOT of money. So a new hardware company can offer these chips/extensions with a fraction of the current license costs. If they start to gouge you, then a another new company can pop up using the same ISA, because there's nothing stopping anyone from using and selling chips of this ISA unlike today. This isn't a end all of proprietary hardware design, which is a good thing because there is a chance for good competition.
majewsky 9y ago
My understanding is, if the ISA is open, it's not nearly as important if the CPU design itself is not, because you can always choose another vendor. Having said that, there are open-source designs for RISC-V CPUs. If you have a FPGA lying around, you can compile BOOM [1] for it and have Linux running on that, although not at particularly impressive speeds of course. There's also lowRISC [2], which is working on a mass-produced development board with an open-source RISC-V CPU, in a format similar to a Raspberry PI. Their timeline says that they hope to be ready for crowd-funding the initial production run sometime this year. [1] https://github.com/ucb-bar/riscv-boom https://github.com/ucb-bar/riscv-boom [2] http://www.lowrisc.org/ http://www.lowrisc.org/
microcolonel 9y ago
There are some interesting open CPU designs at the high level, but it is basically impossible to fab a state of the art chip with truly open designs. From the standard cells down, you are unlikely to be allowed to know anything. Bunnie Huang touched on this, and other themes, at the 6th workshop (though sadly the audio was not captured directly from the microphone, so it's crummy PA sound from the perspective of the camera): https://www.youtube.com/watch?v=zXwy65d_tu8 https://www.youtube.com/watch?v=zXwy65d_tu8 That said, if you mean the high level/functional design of the chip, then there are quite a few open ones. Chris Celio is working on a (seemingly quite excellent) superscalar out of order RISC-V called BooM. There's a reference in-order core called Rocket, which is attacked to a lot of "uncore" infrastructure which is reused by BooM and a couple other chips. They also have an introductory educational RISC-V core called Sodor. There's Z-scale which is a deeply-embedded-sized in-order core. Clifford Wolf, in addition to developing a formal verification framework for RISC-V cores, has a small RISC-V core called PicoRV32. SiFive's FE310 is open to the extent permitted by the agreements they've had to make to fab the chips, which includes RTL for the core itself and a couple other things. FE310 being the model they shipped in their Arduino-compatible HiFive1 boards.

Ok, so the ISA is open. What about the rest of the design of the CPU?

by ant6n 9y ago

Ok, so the ISA is open. What about the rest of the design of the CPU?

ktta 9y ago

BSD license means that any company which uses this ISA doesn't have to. So you won't be seeing any completely open GPUs or CPUs by Nvidia or AMD. That's because the architecture is a huge part of where the work goes into. All this project is trying to do is to democratize the ISA. Which means, once the big companies start using this ISA, the ISA will get popular. Then a small company can release a niche chip and not have to pay anything. Examples: Microsoft Hololens uses Xtensa architecture - which is expensive and the support is apparently terrible. Nvidia's Tegra chip uses ARM's ISA and makes it's own modifications, but still has to pay a LOT of money. So a new hardware company can offer these chips/extensions with a fraction of the current license costs. If they start to gouge you, then a another new company can pop up using the same ISA, because there's nothing stopping anyone from using and selling chips of this ISA unlike today. This isn't a end all of proprietary hardware design, which is a good thing because there is a chance for good competition.

majewsky 9y ago

My understanding is, if the ISA is open, it's not nearly as important if the CPU design itself is not, because you can always choose another vendor. Having said that, there are open-source designs for RISC-V CPUs. If you have a FPGA lying around, you can compile BOOM [1] for it and have Linux running on that, although not at particularly impressive speeds of course. There's also lowRISC [2], which is working on a mass-produced development board with an open-source RISC-V CPU, in a format similar to a Raspberry PI. Their timeline says that they hope to be ready for crowd-funding the initial production run sometime this year. [1] https://github.com/ucb-bar/riscv-boom https://github.com/ucb-bar/riscv-boom [2] http://www.lowrisc.org/ http://www.lowrisc.org/

microcolonel 9y ago

There are some interesting open CPU designs at the high level, but it is basically impossible to fab a state of the art chip with truly open designs. From the standard cells down, you are unlikely to be allowed to know anything. Bunnie Huang touched on this, and other themes, at the 6th workshop (though sadly the audio was not captured directly from the microphone, so it's crummy PA sound from the perspective of the camera): https://www.youtube.com/watch?v=zXwy65d_tu8 https://www.youtube.com/watch?v=zXwy65d_tu8 That said, if you mean the high level/functional design of the chip, then there are quite a few open ones. Chris Celio is working on a (seemingly quite excellent) superscalar out of order RISC-V called BooM. There's a reference in-order core called Rocket, which is attacked to a lot of "uncore" infrastructure which is reused by BooM and a couple other chips. They also have an introductory educational RISC-V core called Sodor. There's Z-scale which is a deeply-embedded-sized in-order core. Clifford Wolf, in addition to developing a formal verification framework for RISC-V cores, has a small RISC-V core called PicoRV32. SiFive's FE310 is open to the extent permitted by the agreements they've had to make to fab the chips, which includes RTL for the core itself and a couple other things. FE310 being the model they shipped in their Arduino-compatible HiFive1 boards.