For PCIe with essentially baseband signaling and short links the bottleneck is in the transistors. It's in balancing the power requirements with cost/manufactur

For PCIe with essentially baseband signaling and short links the bottleneck is in the transistors. It's in balancing the power requirements with cost/manufacturability of the link interface circuitry. Both for power consumption and EMC reasons you want to minimize the maximum slew rate of the signal on the link (and thus the voltage) while on the same hand you need the voltage to stay large enough so that the receiver (which is for all purposes an analog design) can be implemented in widespread digital CMOS processes. On the other hand both conventional parallel PCI and conventional (<=2.0) USB is limited by physical factors, which is in both cases the physical length of the link/bus and propagation velocity of the used wires (ie. speed of light divided by some small-ish constant). In both these standards this limit was intentionally introduced by Intel as cost reducing measure (in PCI's case this means that motherboard does not have to contain about 60 or so discrete resistors, real impact on cost of USB's implementation is somewhat questionable).