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Can someone enlighten me on what is the bottleneck for the transfer speed from hardware point. Is it the material used in the wire, or the transistors or some o
by likelynew 9y ago
Can someone enlighten me on what is the bottleneck for the transfer speed from hardware point. Is it the material used in the wire, or the transistors or some other thing? And, also since the transfer speed is continuously increasing, what are the improvements in the hardware over, say, last 10 years.
- jfoutz 9y agoI'm not even remotely qualified to answer. But anyway, a charge moving down a wire makes a magnetic field. Sending little packets of 0 or 1 means there's a lot of little fields forming and collapsing around the wire. Motherboards are very small, so that field may be big enough to push up against the field of the next wire. That's the bottleneck. electrons in a conductor are crazy fast (i think a big fraction of c). The problem is sending enough of them that you get a meaningful signal, but not so many they interfere with their neighbors. i'd guess the speed improvements come from much more precise timing and voltages, so you can get better guarantees about interference. if voltage is +/-10%, that field will be bigger, and interfere more. If the timings are +/-10% the field will be there when you don't want it to for the next signal. Anyway, i'm sure there are much more knowledgeable people who can give you much better insight, but i think that's the physics 101 kinda answer.
- xyzzyz 9y agoElectrons in the conductor are actually kinda slow, it's on the order of millimeters or centimeters per second. It's the electromagnetic field propagation that is fast. That is, if you have a conductor cable, and apply voltage to it, the individual electrons inside it will proceed very slowly, but they all will start moving almost at the same time along the length of the wire.
- bedros 9y agono way electrons speed is at centimeters or even millimeters per second, electrons travel at or close to speed of light.
- azernik 9y agoThis is factually false: https://en.wikipedia.org/wiki/Drift_velocity https://en.wikipedia.org/wiki/Drift_velocity
- jzwinck 9y agoYou're both right. Individual electrons can move at high speeds (not c), but the overall flow of electrons in a wire is very slow. This happens because individuals move in random directions but the group has a slow push with the current. Imagine people going to the shopping mall. Once in a while someone goes in and an hour or two later they come out the other door 10m away. But they travelled a lot more than 10m. You just didn't notice from outside.
- mbell 9y ago> Individual electrons can move at high speeds (not c) My memory may be off but as I recall the fermi speed in copper is only around 0.5% of c, rather far off. What does propagate at speeds on the order of c is the EM field, which is what most people are actually talking about when they think of electricity moving down a wire. But, it's still something around ~60% of c in a copper transmission line.
- bedros 9y agothis is actually correct, electric signals are actually about 6inches or 15cm per nano second (not seconds) https://en.wikipedia.org/wiki/Signal_velocity https://en.wikipedia.org/wiki/Signal_velocity
- mbell 9y agoYou're describing the EM field, not the electrons themselves. Actually the two are moving in opposite directions as well.
- GuB-42 9y agoElectrons move fast, though not nearly as fast of the speed of light. However, they don't go in a straight line. So if you mark a single electron and look at it from afar, you will see it move very slowly. But if you look closer, you will see it jiggling around with a slight bias toward a direction. What goes at nearly the speed of light is the "message" that electrons should move a certain way. If you want an analogy, if you blow into a flute, even though the air is moving slowly, the sound travels fast.
- mbell 9y agoPCIe uses differential signaling which should approximate AC so the electrons do not have a net movement down the wire at all, they more or less just wiggle back and forth. In reality there is likely some DC bias resulting net migration but a signal trace should be very low current; you're probably looking at electron drift velocities in the range of a 1-2 millimeters per hour if were to hand-wave a guess.
- dghughes 9y agoThe way I like to visualize it is a line of billiard balls. You smack one end and all balls move a bit maybe one place over but the force (charge) moves through them moving the last ball. (Yes charge isn't force but can be made into a electromotive force EMF via inductors, coils etc.).
- jhoechtl 9y agoThis is also a flawed analogy as the whole line of balls will still move slow. It's more like tiny balls on a loudspeaker. When you apply energy to the loudspeaker a pattern depending on energy on frequency will develop. It's more the speed at which this pattern can change rather the speed of movement of the individual balls
- dghughes 9y agoI'm thinking more along the lines of the spot where the balls were is a hole which the balls now occupy. The balls moving isn't the point I was trying to make it was the force from one end to the other. Not the greatest analogy I'll admit. I'm not sure I understand what you're saying it almost sounds like you're referring to impedance.
- signa11 9y agoone possible way to think about it is to realize that all wires can be modeled as a transmission line (most accurately) with finite (but non-zero) R(esistance), L(inductance) and C(capacitance) components. signals propagate over the transmission line as a wave by alternatively transferring energy from electric to the magnetic fields i.e. between L & C. which is where the delay comes from... it is fairly trivial to derive the wave propagation equation for the above model (assuming ofcourse that leakage conductance is zero). when considering lossy transmission lines though, things get quite complicated, but you can always (almost) get away with numerical techniques...
- metaphor 9y agoNot precisely sure wrt PCIe 4.0, but I'd speculate that bandwidth limits of copper on FR4 is surely one contributing factor, driven by a cost-sensitive consumer market. Cost-optimized interconnect solution may also be another. Somewhat related, I've noticed comm tech tends to follow a fairly consistent evolution: new enabling material/process, improvements to interconnect, algorithm optimizations, repeat.
- dfox 9y agoFor PCIe with essentially baseband signaling and short links the bottleneck is in the transistors. It's in balancing the power requirements with cost/manufacturability of the link interface circuitry. Both for power consumption and EMC reasons you want to minimize the maximum slew rate of the signal on the link (and thus the voltage) while on the same hand you need the voltage to stay large enough so that the receiver (which is for all purposes an analog design) can be implemented in widespread digital CMOS processes. On the other hand both conventional parallel PCI and conventional (<=2.0) USB is limited by physical factors, which is in both cases the physical length of the link/bus and propagation velocity of the used wires (ie. speed of light divided by some small-ish constant). In both these standards this limit was intentionally introduced by Intel as cost reducing measure (in PCI's case this means that motherboard does not have to contain about 60 or so discrete resistors, real impact on cost of USB's implementation is somewhat questionable).
- aidenn0 9y agosee nuand's response for some other interesting things; remember that it's baseband being transmitted over a bandwidth-limited channel, so equalizaiton and shaping of the pulses can significantly affect the throughput at a given BER.
- bedros 9y agoI'm no expert on pcie signaling, but I have some general idea, problems are how to take care of the electromagnetic noise, that's why PCIe uses differential pairs wiring (both positive and negative wires are next to each other on board) instead of single-ended (single wire with common ground, negative) which were used in original PCI and PCI-X so the if some noise hits the first wire, same noise hits the second differential wire. improvements in coding and decoding the signals with error correction also help recovering any errors caused by the electromagnetic noise.
- nuand 9y agoTake a look at slides 9 through 15 of this presentation: https://pcisig.com/sites/default/files/files/PCI_Express_Electrical_Basics.pdf https://pcisig.com/sites/default/files/files/PCI_Express_Ele... PCIe signals are generated by transceivers -- devices within chips that are specialized in signal conditioning e.g echo cancelling, emphasis/de-emphasis, dynamic impedance matching. These transceivers and the analog and digital techniques they implement get better with time. This is easily measurable by looking at the Bit Error Rate of data or by looking at eye diagrams (see slide 15). As data rates increase things like drive strengths, impedance mismatches, and a number of other properties of silicon will "close the eye" meaning the transmitted "0"s and "1"s are not different enough for them to be distinguished by a receiver enough of the time to successfully decode a packet. (PCIe is packet based, it's surprisingly somewhat similar to Ethernet). But essentially as our understanding and processes for manufacturing semiconductor devices increase, we're able to "open the eye" more, at which point the industry decides to increase data rates.
- aidenn0 9y agoThe TL;DR is that there's no silver bullet but lots of lead bullets. The big gains in PCIe from generation to generation are the result of accumulating lots of smaller gains in other places. It helps that this isn't happening just for PCIe; there's lots of breakthroughs that benefit (and may have originated with) other high speed links.
- bicubic 9y agoWould these problems persist if we switched to optical signaling instead of rf? Can we expect an optical PCIe equivalent one day?
- deleted 9y ago[deleted]
- pjc50 9y agoThe nature of problems is different, but fundamentally the two questions of "how to distinguish between 1 and 0 in the presence of noise" and "can the reciever and transmitter change state fast enough" apply. Optical PCIe would be hugely handicapped by lack of a standard optical PCB construction method. You'd have to print waveguides onto the PCB. And then it stops working if you get dust in the socket.
- deleted 9y ago[deleted]
- kabdib 9y agoGen1 to Gen2 doubled the clock rate from 2.5 Gb to 5.0Gb. Gen2 to Gen3 increased the clock to 8 Gb, but also reduced the encoding overhead (from 8->10 to 128->130). There were some tweaks to the electrical level of things as well. The electrical level isn't too magic, but there are still a lot of things that have to be tuned (the chapter on tuning in the Mindshare book on PCIe is about 100pp). For a commodity consumer bus, the relative reliability and speed of PCIe is kind of a miracle.